AD9277

PRODUCTION

Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator

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Overview

  • 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator
  • Low noise preamplifier (LNA) - Please see data sheet for additional information.
  • Variable gain amplifier (VGA)
    Attenuator range: −42 dB to 0 dB
    Postamp gain: 21 dB/24 dB/27 dB/30 dB
    Linear-in-dB gain control
  • Antialiasing filter (AAF)
    Programmable second-order LPF from 8 MHz to 18 MHz
    Programmable HPF
  • Analog-to-digital converter (ADC) - Please see data sheet for additional information.
  • CW mode I/Q demodulator
    Individual programmable phase rotation
    Output dynamic range per channel >160 dBFS/√Hz
  • Low power: 207 mW per channel at 14 bits/50 MSPS (TGC), 94 mW per channel for CW Doppler
  • Flexible power-down modes
  • Overload recovery in <10 ns
  • Fast recovery from low power standby mode: <2 μs
  • 100-lead TQFP_EP

The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.

Each channel features a variable gain range of 42 dB, a fully differ-ential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.

The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.

The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.

Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.

Fabricated in an advanced CMOS process, the AD9277 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C.

Applications

  • Medical imaging/ultrasound
  • Automotive radar

AD9277
Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator
AD9277-fbL AD9277-pc AD9277 Typical Application Diagram
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Tools & Simulations

AD9277 IBIS Models 1

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool

Evaluation Kits

eval board
HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Details

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

EVAL-AD9277

AD9277 Evaluation Board

Product Details

This page contains evaluation board documentation and ordering information for evaluating the AD9277.

HSC-ADC-EVALCZ
FPGA-Based Data Capture Kit
High_Speed_ADC_evalboard_05
EVAL-AD9277
AD9277 Evaluation Board

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