AD9219
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AD9219

Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter

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Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 3
1ku List Price Starting From $18.75
Features
  • 4 ADCs integrated into 1 package
  • 94 mW ADC power per channel at 65 MSPS
  • SNR = 60 dB (to Nyquist)
  • ENOB = 9.7 bits
  • SFDR = 78 dBc (to Nyquist)
  • Excellent linearity
    DNL = ±0.2 LSB (typical)
    INL = ±0.3 LSB (typical)
  • Serial LVDS (ANSI-644, default)
    Low power, reduced signal option (similar to IEEE 1596.3)
  • Data and frame clock outputs
  • 315 MHz full-power analog bandwidth
  • 2 V p-p input voltage range
  • 1.8 V supply operation
  • Serial port control
    Full-chip and individual-channel power-down modes
    Flexible bit orientation
    Built-in and custom digital test pattern generation
    Programmable clock and data alignment
    Programmable output resolution
    Standby mode

Additional Details
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The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con- verter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).

The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

  1. Small Footprint. Four ADCs are contained in a small, space-saving package.
  2. Low power of 94 mW/channel at 65 MSPS.
  3. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation.
  4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.
  5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit).

Applications

  • Medical imaging and nondestructive ultrasound
  • Portable ultrasound and digital beam-forming systems
  • Quadrature radio receivers
  • Diversity radio receivers
  • Tape drives
  • Optical networking
  • Test equipment
  • Part Models 3
    1ku List Price Starting From $18.75

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    Documentation

    Documentation

    Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
    AD9219ABCPZ-40
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    AD9219ABCPZ-65
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    AD9219ABCPZRL7-40
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    Product Lifecycle

    PCN

    Sep 13, 2017

    - 16_0077

    CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.

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    PCN

    Sep 13, 2017

    - 16_0077

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    CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.

    Evaluation Kit

    Evaluation Kits 2

    EVAL-AD9219

    AD9219 Evaluation Board

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    HSC-ADC-EVALCZ

    FPGA-Based Data Capture Kit

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    HSC-ADC-EVALCZ

    FPGA-Based Data Capture Kit

    FPGA-Based Data Capture Kit

    Features and Benefits

    • 64kB FIFO Depth
    • Works with single and multi-channel ADCs
    • Use with VisualAnalog® software
    • Based on Virtex-4 FPGA
    • May require adaptor to interface with some ADC eval boards
    • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
    • DDR Encode Rates on each channel

    Product Detail

    The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
    Tools & Simulations

    Tools & Simulations 4

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