Features and Benefits
- Parallel LVDS (DDR) outputs
- In-band SFDR = 82 dBFS at 340 MHz (500 MSPS)
- In-band SNR = 67.8 dBFS at 340 MHz (500 MSPS)
- 1.1 W total power per channel at 500 MSPS (default settings)
- Noise density = −153 dBFS/Hz at 500 MSPS
- 1.25 V, 2.50 V, and 3.3 V dc supply operation
- Flexible input range: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
- 95 dB channel isolation/crosstalk
- Amplitude detect bits for efficient automatic gain control (AGC) implementation
- Noise shaping requantizer (NSR) option for main receiver function
- See data sheet for additional features
The AD6679 is a 135 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6679 is optimized for wide input bandwidth, high sampling rates, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
- Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
This user guide describes the AD6679 evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. The application software used to interface with the devices is also described. The HSC-ADC-EVALEZ is the recommended FPGA based data capture board for the AD6679. The ADS7-V2EBZ may alternatively be used as the FPGA based data capture board for the AD6679.
The AD6679 data sheet provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to email@example.com.
- Analog signal source and antialiasing filter
- Sample clock source
- 12V, 6.5A switching power supply (supplied with the HSC-ADC-EVALEZ or the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ)
- PC running Windows®
- USB 2.0 port
- AD6679-500EBZ board
- HSC-ADC-EVALEZ FPGA-base data capture kit
- ADS7-V2EBZ FPGA-based data capture kit (optional, but not required)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
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Pricing displayed is based on 1-piece.
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.