Quad IF Receiver

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Part Details
Part Models 2
1ku List Price Starting From $171.54
  • 11-bit 200MSPS output data rate per channel
  • Integrated Noise Shaping Requantizer (NSR)
  • Performance with NSR enabled:
    SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
    SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
  • Performance with NSR disabled:
    SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
    SFDR: 83 dBc to 70 MHz @ 185 MSPS
  • Low power: 1.2 W @ 185 MSPS
  • 1.8 V analog supply operation
  • 1.8 V LVDS (ANSI-644 levels) output
  • 1-to-8 integer clock divider
  • Internal ADC voltage reference
  • 1.75 V p-p analog input range (programmable to 2.0 V p-p)
  • Differential analog inputs with 800 MHz bandwidth
  • See data sheet for additional features
Additional Details
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The AD6657 is an 11-bit, 200 MSPS, quad-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of four high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6657 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6657 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6657 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6657 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired.

After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels.

The AD6657 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.

Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing.

The AD6657 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of −40°C to +85°C.


  • Communications
  • Diversity radio and smart antenna (MIMO) systems
  • Multimode digital receivers (3G)
     WCDMA, LTE, CDMA2000
  • I/Q demodulation systems
  • General-purpose software radios


  1. Four ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
  2. Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.
  3. LVDS digital output interface configured for low cost FPGA families.
  4. 230 mW per ADC core power consumption.
  5. Operation from a single 1.8 V supply.
  6. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.
  7. On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems.

Part Models 2
1ku List Price Starting From $171.54

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Evaluation Kit

Evaluation Kits 2


AD6657 Evaluation Board

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FPGA-Based Data Capture Kit



FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Tools & Simulations

Tools & Simulations 3

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