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Features
- High performance
- Throughput: 2 MSPS (AD4630-24) or 500 kSPS (AD4632-24) per channel maximum
- INL: ±0.9 ppm maximum from −40°C to +125°C
- SNR: 105.7 dB typical
- THD: −127 dB typical
- NSD: −166 dBFS/Hz typical
- Low power
- 15 mW per channel at 2 MSPS
- 5 mW per channel at 500 kSPS
- 1.5 mW per channel at 10 kSPS
- Easy Drive features reduce system complexity
- Low 0.6 μA input current for dc inputs at 2 MSPS
- Wide input common-mode range: −(1/128) × VREF to +(129/128) × VREF
- Flexible external reference voltage range: 4.096 V to 5 V
- Accurate integrated reference buffer with 2 μF bypass capacitor
- Programmable block averaging filter with up to 216 decimation
- Extended sample resolution to 30 bits
- Overrange and synchronization bits
- Flexi-SPI digital interface
- 1, 2, or 4 SDO lanes per channel allows slower SCK
- Echo clock mode simplifies use of digital isolator
- Compatible with 1.2 V to 1.8 V logic
- 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply and reference capacitors to help reduce system footprint
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The AD4630-24/AD4632-24 are two-channel, simultaneous sampling, Easy Drive™, 2 MSPS or 500 kSPS successive approximation register (SAR) analog-to-digital converters (ADCs). With a guaranteed maximum ±0.9 ppm INL and no missing codes at 24 bits, the AD4630-24/AD4632-24 achieve unparalleled precision from −40°C to +125°C. Figure 1 in the data sheet shows the functional architecture of the AD4630-24/AD4632-24.
A low drift, internal precision reference buffer eases voltage reference sharing with other system circuitry. The AD4630-24/ AD4632-24 offer a typical dynamic range of 106 dB when using a 5 V reference. The low noise floor enables signal chains requiring less gain and lower power. A block averaging filter with programmable decimation ratio can increase dynamic range up to 153 dB. The wide differential input and common-mode ranges allow inputs to use the full voltage reference (±VREF) range without saturating, simplifying signal conditioning requirements and system calibration. The improved settling of the Easy Drive analog inputs broadens the selection of analog front-end components compatible with the AD4630-24/AD4632-24. Both single-ended and differential signals are supported.
The versatile Flexi-SPI serial peripheral interface (SPI) eases host processor and ADC integration. A wide data clocking window, multiple SDO lanes, and optional dual data rate (DDR) data clocking can reduce the serial clock to 10 MHz while operating at a sample rate of 2 MSPS or 500 kSPS. Echo clock mode and ADC host clock mode relax the timing requirements and simplify the use of digital isolators.
The 64-ball chip scale package ball grid array (CSP_BGA) of the AD4630-24/AD4632-24 integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout.
APPLICATIONS
- Automatic test equipment
- Digital control loops
- Medical instrumentation
- Seismology
- Semiconductor manufacturing
- Scientific instrumentation
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AD4632-24
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| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD4632-24BBCZ |
64-Lead BGA (7 mm x 7 mm x 1.72 mm)
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| AD4632-24BBCZ-RL |
64-Lead BGA (7 mm x 7 mm x 1.72 mm)
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- AD4632-24BBCZ
- Pin/Package Drawing
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64-Lead BGA (7 mm x 7 mm x 1.72 mm)
- Documentation
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Material Declaration
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HTML
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SamacSys
- AD4632-24BBCZ-RL
- Pin/Package Drawing
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64-Lead BGA (7 mm x 7 mm x 1.72 mm)
- Documentation
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HTML
Material Declaration
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HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
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Ultra Librarian
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SamacSys
Software & Part Ecosystem
Device Drivers
FPGA/HDL
Looking for Evaluation Software? You can find it here
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 1
EVAL-AD4630-24
AD4630-24 SAR ADC Evaluation Board
Product Detail
The EVAL-AD4630-24FMCZ evaluation board enables quick and easy evaluation of the AD4630 family of 24-bit precision successive approximation register (SAR) analog-to-digital converters (ADCs).
The AD4630-24 is a low power, 24-bit, 2-channel, 24-bit precision SAR ADC that supports up to 2 MSPS per channel. The evaluation board demonstrates the performance of the AD4630-24 and provides a configurable analog front end (AFE) for a variety of system applications.
The EVAL-AD4630-24FMCZ evaluation board is designed for use with the Digilent ZedBoard™. The ZedBoard is used to control data capture and buffering. The evaluation board connects to the ZedBoard board via a field-programmable gate array (FPGA) mezzanine card (FMC) low pin count (LPC) connector. The ZedBoard hosts a Xilinx Zynq7000 SoC, which has two processor cores and programmable FPGA fabric. The ZedBoard connects to the PC through USB.
APPLICATIONS
- Automatic test equipment
- Digital control loops
- Medical instrumentation
- Seismology
- Semiconductor manufacturing
- Scientific instrumentation
Resources
Evaluation Kits1
Tools & Simulations 4
LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.
To launch ready-to-run LTspice demonstration circuits for this part:
Step 1: Download and install LTspice on your computer.
Step 2: Click on the link in the section below to download a demonstration circuit.
Step 3: If LTspice does not automatically open after clicking the link below, you can instead run the simulation by right clicking on the link and selecting “Save Target As.” After saving the file to your computer, start LTspice and open the demonstration circuit by selecting ‘Open’ from the ‘File’ menu.
Lt Spice
Precision ADC Driver Tool
Signal Chain Designer - BETA
IBIS Model 1
