What will the output data from an ADC look like during an overrange event?
Every once in a while someone, usually an older engineer, asks what a particular converter’s output data will be during an overrange event. The first time I heard the question (many years ago!), I thought it was silly. Then a colleague with a bit more experience explained that early integrated ADCs typically exhibited a behavior known as rollover.
Most modern high-speed ADCs include an overrange (OR) flag. This output bit, which is usually synchronous with the converter’s output data, indicates that the analog input sample exceeded the converter’s full-scale input range. Consider an ADC with offset binary coding. If the input signal exceeded the converter’s positive full-scale range, the ADC would clip, and the output data would be all 1’s (1111 1111 1111 for a 12-bit ADC). If the input exceeded its negative full-scale range, the output would be all 0’s (0000 0000 0000 for a 12-bit ADC). In each case, the OR bit would be set, indicating that the input had been out of range during that sample.
In contrast, with older converters that exhibited rollover, a 12-bit converter whose input was at positive full scale + 1 LSB might have an output of 0000 0000 0001 instead of all 1’s. The user would know from the OR output that the ADC had been overranged and that the data should be ignored. These bits would have been the correct lower 12 bits for a 13-bit converter with twice the input range, but for a 12-bit converter, this output would indicate that the input was 1 LSB above negative full scale. You can imagine how this could cause a problem in any system.
Rest assured that you won’t have to deal with this problem when using one of ADI’s high-speed converters. I’ve been working on these products since the 1980s, and we haven’t released a product with this concern in all those years. A few engineers must have burned by this back in the day, and are dotting their i’s and crossing their t’s to make sure they don’t get burned again.
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