Capacitor banks are used to filter noise and provide energy storage for fast load transient response. For modeling the stability of a DC/DC converter the ESR of the capacitor bank is needed. This can be easily done if only one type of capacitor is used with multiple capacitors in parallel. This is difficult if many different types of capacitors are used in a parallel configuration. Using LTspice, the capacitor bank can be characterized and key parameters can be extracted. This is very helpful when using the LTpowerCAD tool for stability analysis.
In the schematic below, five different capacitors are in parallel. For stability analysis, it is desired to model this as one capacitor.
Running the simulation, the impedance is plotted below. This is simply the source voltage divided by the source current; V(n001)/I(V1).
Using the curser measurement tool, the self-resonant frequency of the network is 243KHz, and the amplitude of the impedance is –49.65dB. It is important to note at self-resonance the imaginary impedance of the capacitive reactance and the inductive reactance cancel resulting in the ESR of the LC network as the only impedance. Solving for the impedance in Ohms, the resultant ESR is 3.29m Ω.
Quick note on algebra:
20log(x) = –49.65
log(x) = –2.4825
x = 0.00329
A couple of other insights can be gained from this impedance approach. The plot below shows the current in two of the capacitors, I(C3) and I(C4), as a function of frequency. This is intuitively obvious, but helpful to quantify. The 4.7µF ceramic capacitor has a low impedance up to 2.3MHz, whereas the 330µF capacitor is inductive at 2.3MHz and provides a higher impedance for energy transfer compared to the 4.7µF capacitor.
By using LTspice to characterize the self-resonance of a bank of parallel capacitors the equivalent ESR can be easily determined. LTspice is a powerful tool that provides an easy format for defining the problem, and an intuitively obvious graphical solution that allows a simple analysis for a complex problem.