MAX3878

2.5Gbps、+3.3V时钟与数据再定时IC，带有垂直调节阈值

数据手册 (Rev. 0)

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产品详情

Exceeds ANSI, ITU, and Bellcore SONET/SDH Specifications
Adjustable Input Threshold (±180mV)
10mVp-p to 1.2Vp-p Differential Input Range
540mW Power Dissipation (at +3.3V)
Fully Integrated Clock Recovery and Data Retiming
Optional Holdover Capability (Using External Reference Clock)
0.003UI_RMS Clock Jitter Generation
Tolerates >2000 Consecutive Identical Digits
Additional 2.488Gbps Input for Diagnostic Loopback Testing
Differential PECL or CML Data and Clock Outputs
Loss-of-Signal Indicator
Loss-of-Lock Indicator

参考资料

数据手册 2

MAX3877-MAX3878: 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust Data Sheet (Rev.0) 06/28/2001

3006: 2.5Gbps、+3.3V时钟与数据再定时IC，带有垂直调节阈值 Data Sheet 01/01/1900

可靠性数据 1

MAX3878 Reliability Data 01/12/2023

应用笔记 2

HFAN-04.0.3: Jitter in Digital Communication Systems, Part 1 09/07/2001

HFAN-04.0.2: Converting between RMS and Peak-to-Peak Jitter at a Specified BER 12/07/2000

这是最新版本的数据手册

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