AD9088

预发布

Apollo MxFE Octal, 16-Bit, 16 GSPS RF DAC and Octal, 12-Bit, 8 GSPS RF ADC

数据手册 (Rev. PrA) 产品选型表
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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产品详情

  • Flexible reconfigurable common platform design
    • 8 DACs and 8 ADCs (8D8A)
    • Usable RF analog bandwidth to 16 GHz
    • Maximum DAC/ADC sample rate up to 16 GSPS/8 GSPS
  • DAC to ADC sample rate ratios of 1 and 2
    • Clocking
    • On-chip PLL (7 GHz to 14 GHz VCO)
  • External RFCLK input up to 8 GHz
    • Multichip synchronization
  • Single-ended (SE) ADC inputs
    • 50 Ω input impedance
    • Integrated on-chip wide bandwidth balun
  • ADC AC performance at 8 GSPS
    • Full-scale input voltage: 650 mV p-p/0.3 dBm
    • Noise density: −148 dBFS/Hz at −20 dBFS at 2 GHz
    • HD2/HD3: −70 dBFS/−75 dBFS at −7 dBFS at 2 GHz
    • IMD3: −75 dBFS at −13 dBFS/tone at 2 GHz
  • DAC AC performance at 16 GSPS
    • Full-scale output power: −1.1 dBm at 2 GHz
    • IMD3: −7 5 dBc at −13 dBFS/tone at 2 GHz
    • NSD (shuffling disabled): −163 dBFS/Hz at −1 dBFS at 2 GHz
    • NSD (shuffling enabled): −158 dBFS/Hz at −1 dBFS at 2 GHz
  • Versatile digital features
    • Supports real or complex digital data (8-, 12-, 16-bit)
    • Configurable DDC and DUC
    • 16 fine complex DUCs and 8 coarse complex DUCs
    • 16 fine complex DDCs and 8 coarse complex DDCs
    • Option to bypass fine and coarse DUC/DDC
    • DUC/DDC alias rejection
    • 85 dB for interpolation filters
    • 100 dB for decimation filters
  • Programmable FIR filters for transmit/receive.
  • Dynamic configuration through SPI/HSCI/GPIO
  • Interface
    • SPI
    • High-Speed Control Interface
    • JESD204B/JESD204C: 20 Gbps/32.5 Gbps
  • 24 lanes for Rx, 24 lanes for Tx
  • Signal monitor for slow AGC control
  • Auxiliary features
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • TDD power savings option
  • Total power consumption dependent on device configuration: 14 W to 20 W typical
  • 24 mm × 26 mm, 889-ball BGA with 0.8 mm pitch
  • Operating junction temperature (TJ): −40°C to +110°C
AD9088
Apollo MxFE Octal, 16-Bit, 16 GSPS RF DAC and Octal, 12-Bit, 8 GSPS RF ADC
AD9088 Functional Block Diagram
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参考资料

数据手册 1

技术文章 3

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硬件生态系统

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eval board
schematic 1
schematic 2
schematic 3
ADS10-V1EBZ

ADS10-V1EBZ Evaluation Board

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特性和优点

Xilinx Virtex Ultrascale+ XCVU35P-3FSHV2892E FPGA.

  • One (1) FMC+ connector.
  • Twenty (24) 32.75Gbps transceivers supported by one (1) FMC+ connector.
  • On-board HBM DRAM in FPGA.
  • Simple USB 3.0 port interface.

产品详情

When connected to a specified Analog Devices high speed converter evaluation board, the ADS10-V1EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS10-V1EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.

ADS10-V1EBZ
ADS10-V1EBZ Evaluation Board
ADS10-V1EBZ - Top View ADS10-V1EBZ - Bottom View ADS10-V1EBZ - Angle View

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