AD4083
推荐用于新设计16-Bit, 40MSPS, Low Noise, Low Power SAR ADC
- 产品模型
- 3
概述
- 16-bit resolution, no missing codes
- Throughput: 40MSPS, 48.43ns conversion latency
- Noise spectral density: 10.69nV/√Hz,165.9dBFS/Hz
- Low 1/f, low frequency noise (0.1Hz to 10Hz): 265nV rms
- Low Power:70.2mW typical at 40MSPS
- INL: ±8ppm (typ), ±12ppm (max)
- Dynamic range: 92.94dBFS
- SNR/THD
- 92.2dB (typ)/−111dB (typ) at fIN = 1kHz
- 92dB (typ)/−103.4dB (typ) at fIN = 1MHz
- Easy Drive
- 6V p-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current
- Integrated, low-drift reference buffer and decoupling
- Integrated VCM generation
- Digital features and data interface
- Conversion result FIFO, 16K sample depth
- Digital averaging filter with up to 210 decimation
- SPI configuration
- Configurable data interface
- Single lane, DDR, serial LVDS, 640Mbps per lane
- Dual lane, DDR, serial LVDS, 320Mbps per lane
- Single/quad lane SPI data interface
- Package
- 49-ball, 5mm × 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
- Operating temperature range: −40°C to +85°C
The AD4083 is a high speed, low noise, low distortion, 16-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 90dBFS) at signal frequencies in excess of 1MHz enables the AD4083 to service a wide variety of precision, wide bandwidth data acquisition applications. Simplification of the input anti-alias filter design can be accomplished by applying oversampling along with the integrated digital filtering and decimation to reduce noise and lower the output data rate for applications that do not require the lowest latency of the AD4083.
The AD4083 Easy Drive features reduce both signal chain complexity and power consumption while enabling greater channel density and flexibility in companion component selection. The product input structure was designed to minimize any input dependent signal currents, therefore reducing any converter induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements as compared to other high-speed data converters.
The AD4083 includes several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regulators to generate ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can greatly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated in the package to ensure optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint.
APPLICATIONS
- Digital imaging
- Cell analysis
- Spectroscopy
- Automated test equipment
- High speed data acquisition
- Digital control loops, hardware in the loop
- Power quality analysis
- Source measurement units
- Electron and X-ray microscopy
- Radar level measurement
- Nondestructive test
参考资料
数据手册 1
用户手册 1
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| 产品型号 | 引脚/封装图-中文版 | 文档 | CAD 符号,脚注和 3D模型 |
|---|---|---|---|
| AD4083BBCZ | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) | ||
| AD4083BBCZ-RL | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) | ||
| AD4083BBCZ-RL7 | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) |
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