The ADRF6850 evaluation board (EVAL-ADRF6850EB1Z) is designed to allow the user to evaluate all aspects of the ADRF6850. The board comes with a software GUI on a CD which allows the user to write to the complete register set of the ADRF6850 through the parallel port of a PC either via an SPI or I2C interface. It has SMA connectors for the demodulator’s input RF signal (connected for single-ended operation on this board), the output baseband signals, the VGAIN input which controls the gain of the VGA as well as the +3.3V power supplies. It contains a 13.5 MHz reference clock for the reference input of the on-chip PLL and the ability to drive this input with an external reference clock if so desired. It contains a 4th order loop filter for the PLL which is optimized for best rms jitter performance with a 13.5 MHz reference clock and a charge pump current of 2.5 mA. The loop bandwidth is approximately 50 kHz with a phase margin of 55⁰. The PLL frequency and performance can be monitored using the LOMON outputs. These are open-collector outputs and need to be terminated to 3.3V using on-board 50 Ω resistors or pull-up inductors. Lock detect and MUXOUT can also be monitored. All supplies are decoupled by a parallel combination of 100 nF and 56 pF capacitors. Low frequency decoupling is provided by a 10 µF capacitor. More details of the evaluation board is contained in the ADRF6850 datasheet.