Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps propagation delay and adds only 110 fs random jitter (RJ).
The input has a center tapped, 100 Ω, on-chip termination resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS (ac-coupled only). A VREF pin is available for biasing ac-coupled inputs.
The HVDS output stage is designed to directly drive 1.9 V each side into 50 Ω terminated to VCC for a total differential output swing of 3.8 V.
The ADCLK914 is available in a 16-lead LFCSP. It is specified for operation over the extended industrial temperature range of −40°C to +125°C.
- Clock and data signal restoration
- High speed converter clocking
- Broadband communications
- Cellular infrastructure
- High speed line receivers
- ATE and high performance instrumentation
- Level shifting
- Threshold detection
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Solutions Bulletins & Brochures
Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1
Termination of High-Speed Converter Clock Distribution Devices
(The Back Burner, January 2010)
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008)
RF Source Booklet
RF IC Product Overview
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
Clock Requirements For Data Converters
(Electronic Design, 2/2005)