1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.
The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.
Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.
The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.
The AD9511 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.
- Low jitter, low phase noise clock distribution
- Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ Converters
- Wireless infrastructure transceivers
- High performance instrumentation
- Broadband infrastructure
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Product Selection Guide
RF, Microwave, and Millimeter Wave IC Selection Guide 2017
Using a unique combination of design skills, systems understanding, and process technologies, Analog Devices offers...
ADIsimCLK™ Reference Design Files
Once ADIsimCLK is installed, users may take advantage of saved design files with the extension, ".clk".
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