AD9445: 14-Bit, 105 MSPS / 125 MSPS A/D Converter
The AD9445 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, IF sampling track-and-hold circuit and is optimized for power, small size, and ease of use. The product ...More
AD9445: 14-Bit, 105 MSPS / 125 MSPS A/D Converter
Product Description
The AD9445 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, IF sampling track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 105 MSPS conversion rate and is optimized for multi-carrier, multimode receivers, such as those found in cellular infrastructure equipment.
The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.
Optional features allow users to implement various selectable operating conditions, including data format select and output data mode.
The AD9445 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C).
Product Highlights
1. High performance: Outstanding SFDR performance for multicarrier, multimode 3G and 4G cellular base station receivers.
2. Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture.
3. Packaged in a Pb-free, 100-lead TQFP/EP.
4. Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of clock pulse widths.
5. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.
Applications
- Data Sheet Rev 0, 11/2005 (pdf 965kB)
- (About Data Sheets)
Features
- 125 MSPS guaranteed sampling rate (AD9445BSV-125)
- 100 dB two-tone SFDR with 30 MHz and
31 MHz - 73.5 dB SNR with 70 MHz input
- 85 dBc SFDR with 225 MHz input
- Excellent linearity
DNL = ±0.25 LSB typical
INL = ±0.8 LSB typical
- 2.3 W power dissipation
- 3.3 V and 5 V supply operation
- 2.0 V p-p to 3.2 V p-p differential full-scale input
- LVDS outputs (ANSI-644 compatible) or CMOS outputs
- Data format select (Offset Binary or 2’s compliment)
- Output clock available
Verified Circuits Using This Part
Verified Circuits are designed for ease of use and proven to work by ADI applications engineers. To learn more about Verified Circuits from ADI, please visit Verified Circuits Home.
Diagrams
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- Symbols and Footprints
Functional Block Diagram for AD9445
14-Bit, 105 MSPS / 125 MSPS A/D Converter
Other Diagrams for AD9445
14-Bit, 105 MSPS / 125 MSPS A/D Converter
100-Ld TQFP/EP LVDS Mode Pin Configuration
100-ld TQFP/EP CMOS Mode Pin Configuration
Functional Block Diagram for AD9445
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| Part# | Res | Throughput Rate | # of Inputs | Operating Pwr Diss |
|---|---|---|---|---|
| AD9246-125 | 14 | 125MSPS | 1 | 458mW |
| AD9254 | 14 | 150MSPS | 1 | 470mW |
| AD9445-125 | 14 | 125MSPS | 1 | 2.6W |
| AD9640-150 | 14 | 150MSPS | 2 | 938mW |
| AD9261-10 | 16 | 160MSPS | 1 | 473mW |
| AD9230-170 | 12 | 170MSPS | 1 | 407mW |
