AD9430:  12-Bit, 170/210 MSPS 3.3 V A/D Converter

The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is ...More

To drive this ADC in DC-coupled applications, we suggest ADA4937-1 or ADA4938-1. To drive this ADC in AC-coupled applications, we suggest AD8352 or AD8375.

AD9430:  12-Bit, 170/210 MSPS 3.3 V A/D Converter

Product Description

The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference are included on the chip to provide a complete conversion solution.

The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic.

Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate.

Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (-40°C to +85°C).

Applications

  • Wireless and Wired Broadband Communications
  • Cable Reverse Path
  • Communications Test Equipment
  • Radar and Satellite Subsystems
  • Power Amplifier Linearization

    • Features

    • SNR = 65 dB @ Fin up to 70 MHz @
      210 MSPS
    • ENOB of 10.6 @ Fin up to 70 MHz @
      210 MSPS
    • SFDR = 80 dBc @ Fin up to 70 MHz @
      210 MSPS
    • Excellent Linearity:
      - DNL = ±0.3 LSB (Typical)
      - INL = ±0.5 LSB (Typical)
    • Two Output Data Options:
      - Demultiplexed 3.3 V CMOS Outputs Each @ 105 MSPS
      - Interleaved or Parallel Data Output Option
      - LVDS at 210 MSPS
    • 700 MHz Full Power Analog Bandwidth
    • Power Dissipation = 1.3 W Typical @ 210 MSPS
    • 1.5 V Input Voltage Range
    • 3.3 V Supply Operation
    • Output Data Format Option
    • Data Sync Input and Data Clock Output Provided
    • Clock Duty Cycle Stabilizer

    Diagrams

    AD9430 Diagram
    Functional Block Diagram for AD9430

    Specifications

    Resolution (Bits) 12bit
    T-Put Rate 210000000SPS
    # Chan 1
    Supply V Single(+3.3)
    Pwr Diss (max) 1.7W
    Interface LVDS,Par
    Ain Range 1.5 V p-p
    SNR (dB) 65dB
    Pkg Type QFP

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    Part# Res Throughput Rate # of Inputs Operating Pwr Diss
    AD9230-250 12 250MSPS 1 463mW
    AD9430-210 12 210MSPS 1 1.7W
    AD9626-250 12 250MSPS 1 390mW
    AD9211-300 10 300MSPS 1 468mW
    AD9481 8 250MSPS 1 618.8mW
    AD9480 8 250MSPS 1 698mW
    AD9230-170 12