The AD9838 is a low power DDS device capable of producing high performance sine and triangular outputs. It also has an on-board comparator that allows a square wave to be produced for clock generation. Consuming only 11 mW of power at 2.3 V the AD9838 is an ideal candidate for power-sensitive applications.
Capability for phase modulation and frequency modulation is provided. The frequency registers are 28 bits; with a 16 MHz clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz clock rate, the AD9838 can be tuned to 0.02 Hz resolution. Frequency and phase modulation are configured by loading registers through the serial interface and toggling the registers using software or the FSELECT pin and PSELECT pin, respectively.
The AD9838 is written to via a 3-wire serial interface. This serial interface operates at clock rates up to 40 MHz and is compatible with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The analog and digital sections are independent and can be run from different power supplies; for example, AVDD can equal 5 V with DVDD equal to 3 V.
The AD9838 has a power-down pin (SLEEP) that allows external control of the power-down mode. Sections of the device that are not being used can be powered down to minimize current consumption. For example, the DAC can be powered down when a clock output is being generated.
The AD9838 is available in a 20-lead LFCSP_WQ package.
|Title||Content Type||File Type|
|AD9838: 11 mW Power, 2.3 V to 5.5 V, Complete DDS Data Sheet (Rev A, 04/2011) (pdf, 707 kB)||Data Sheets|
|AN-1248: SPI Interface (pdf, 155 kB)||Application Notes|
|AN-1044: Programming the AD5932 for Frequency Sweep and Single Frequency Outputs (pdf, 94 kB)||Application Notes|
|AN-1070: Programming the AD9833/AD9834 (pdf, 127 kB)||Application Notes|
A Technical Tutorial on Digital Signal Synthesis
(pdf, 901 kB)
Copyright © 1999 Analog Devices, Inc.
Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
Performance Clocks: Demystifying Jitter
Join us as we delve into the realm of sub-picosecond jitter clocks. The relationship between jitter and phase noise will be explored in detail and methods for measuring sub-picosecond jitter and ultra low phase noise will be presented and discussed.
|UG-268: Evaluating the AD9838 11 mW Power, 2.3 V to 5.5 V, 16 MHz Complete DDS (pdf, 682 kB)||User Guides|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
|AD9838 FMC-SDP Interposer & Evaluation Board / Xilinx KC705 Reference Design||FPGA HDL||HTML|
|BeMicro FPGA Project for AD9838 with Nios driver||FPGA HDL||HTML|
|AD9838 - Microcontroller No-OS Driver||Device Drivers||HTML|
|AD9834 IIO Direct Digital Synthesis Linux Driver||Device Drivers||HTML|
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