The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The AD9600 has several functions that simplify the automated gain control (AGC) function in a communications receiver. For example, the fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.
In addition, the programmable threshold detector allows monitoring the amplitude of the incoming signal with short latency, using the four fast detect bits of the ADC. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly adjust the system gain to avoid an overrange condition.
Another AGC-related function of the AD9600 is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external 10-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. In addition, flexible power-down options allow significant power savings.
Data Sheet, Rev. B, 12/09
|Title||Content Type||File Type|
|AD9600: 10-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet (Rev B, 12/2009) (pdf, 2990 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
|AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)||Application Notes|
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)||Application Notes|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.