The AD9277 is designed for low cost, low power, small size, and ease of use. It contains eight channels of a variable gain amplifier (VGA) with a low noise preamplifier (LNA); an anti-aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to-digital converter (ADC); and an I/Q demodulator with programmable phase rotation.
Each channel features a variable gain range of 42 dB, a fully differ-ential signal path, an active input preamplifier termination, a maximum gain of up to 52 dB, and an ADC with a conversion rate of up to 50 MSPS. The channel is optimized for dynamic performance and low power in applications where a small package size is critical.
The LNA has a single-ended-to-differential gain that is selectable through the SPI. The LNA input noise is typically 0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred noise of the entire channel is 0.85 nV/√Hz at maximum gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the input SNR is roughly 92 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator. Each demodulator has inde-pendently programmable phase rotation through the SPI with 16 phase settings.
The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO±) for capturing data on the output and a frame clock (FCO±) trigger for signaling a new output byte are provided.
Powering down individual channels is supported to increase battery life for portable applications. A standby mode option allows quick power-up for power cycling. In CW Doppler opera-tion, the VGA, AAF, and ADC are powered down. The power of the TGC path scales with selectable ADC speed power modes.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudo-random patterns, and custom user-defined test patterns entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9277 is available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C.
|Title||Content Type||File Type|
|AD9277: Octal LNA/VGA/AAF/ADC and CW I&Q Demodulator Data Sheet (Rev 0, 08/2009) (pdf, 979 kB)||Data Sheets|
UG-016: Evaluation Board User Guide
(pdf, 2602 kB)
Evaluating the AD9276 and AD9277 Octal LNA/VGA/AAF/12-/14-Bit ADCs and CW I/Q Demodulators
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|Low Cost, Octal Ultrasound Receiver with On-Chip RF Decimator and JESD204B Serial Interface (22 Feb 2013)||Press Releases||HTML|
|AD927x/AD967x Octal Ultrasound Analog Front End (AFE) Product Family Brochure (pdf, 674 kB)||Overview|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD9277 IBIS Models||IBIS Models||HTML|
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.