ADCMP573:  Ultrafast 3.3 V Single-Supply Comparator w/Reduced Swing PECL (RSPECL) Output Drivers

The ADCMP572/ADCMP573 are ultrafast comparators fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers, and the ...More

ADCMP573:  Ultrafast 3.3 V Single-Supply Comparator w/Reduced Swing PECL (RSPECL) Output Drivers

Product Description

The ADCMP572/ADCMP573 are ultrafast comparators fabricated on Analog Devices, Inc.’s proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers.

Both devices offer 150 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs RMS random jitter (RJ). Overdrive and slew rate dispersion is typically less than 15 ps.

A flexible power supply scheme allows either device to operate with a single +3.3 V positive supply and a -0.2 V to +1.2 V input signal range, or with split input/output supplies to support a wider -0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to leave open (on an individual pin basis) for applications requiring high impedance inputs.

The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO - 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided.

The ADCMP572/ADCMP573 are available in a 16-lead LFCSP package.

Features

  • 3.3 V/5.2 V Single-Supply Operation
  • 150 ps Propagation Delay
  • 15 ps Overdrive and Slew Rate Dispersion
  • 8 GHz Equivalent Input Risetime Bandwidth
  • 80 ps Minimum Pulse Width
  • 35 ps Typical Output Rise/Fall
  • 10 ps Deterministic Jitter (DJ)
  • 200 fs Random Jitter (RJ)
  • On-Chip Terminations at Both Input Pins
  • Robust Inputs with No Output Phase Reversal
  • Resistor Programmable Hysteresis
  • Differential Latch Control

Diagrams

ADCMP573 Diagram
Functional Block Diagram for ADCMP573

Specifications

Logic Output PECL
# Per Pkg 1
Prop Delay (ns)typ 0.15ns
Voltage Supply (V) 3.3 to 5
Supply Current (max) 66mA
Min Pulse Width 80ps
Package 16-Lead LFCSP
Output Rise/Fall Time 35 ps
Latch Enable Pin X
Jitter <200 fs

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ADCMP552 0.75 2 60 3.3 to 5 1 -0.2 to Vcc-2V PECL X 700ps
ADCMP553 0.75 1 30 3.3 to 5 1 -0.2 to Vcc-2V PECL - 700ps
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ADCMP572 0.15 1 145 3.3 to 5 1 -0.2 to Vcci-2.1V CML X 80ps
ADCMP573 0.15 1 145 3.3 to 5 1 -0.2 to Vcci-2.1V PECL X 80ps
ADCMP580 0.15 1 240 5, -5.2 2 -2 to 3V CML X 80ps
ADCMP581 0.15 1 240 5, -5.2 2 -2 to 3V