I2C Bus Buffer Resolves Stuck Buses, Eliminates Heavy Load Limitations and Provides Level Translation

Introduction

The I2C bus is a 2-wire bidirectional communications bus primarily used for system configuration and monitoring. A bus master, typically a microcontroller unit (MCU), polls system components for information such as supply voltage and temperature, Vital Product Data (VPD) from memories on removable cards, and system configuration. The master can also use the bus to reconfigure the system through general purpose input/output ports (GPIOs) and other programmable devices. Large-scale telecommunication and data storage systems are divided up into several peripheral cards. Each card plugs on to the I2C bus and communicates its system information to the MCU through the back plane.

Certain considerations must be addressed to ensure a high level of reliability when designing a system using the I2C bus. Primarily, systems must provide protection against a hung or stuck bus. If for any reason the bus is stuck low, there is the potential to bring the entire system down. Another consideration is dealing with heavy capacitive loads on the bus. The I2C standard specifies a 400pF limit on the bus. With systems becoming larger, this specification becomes problematic because of so many devices connected directly to the bus. Systems also need to be robust, allowing cards to be inserted or removed from a live backplane without corruption of the I2C bus data. Finally, cards must be immune to ESD events that can occur from human handling.

The LTC4304 is a multifunctional device. It has a flexible architecture that allows it to be configured into almost any system. The LTC4304 features proprietary stuck bus protection circuitry that unburdens the MCU from the tasks of monitoring, troubleshooting and resolving stuck buses. Simplifying this task also saves PCB board space and connector pins. The LTC4304 provides bidirectional capacitance buffering, isolating the card bus from the backplane bus. Rise time accelerators help heavily capacitive-loaded buses meet I2C rise time specifications. The LTC4304 also enables cards to be inserted or removed from the system without corrupting the data on the I2C bus. Built-in ±15kV of human Body Model ESD protection provides a rugged front end for cards that typically have the SDA and SCL lines connected directly to the card connector.

Circuit Operation

Startup and Hot Swap

To take full advantage of the LTC4304’s Hot Swap features, a staggered connector must be used: where VCC and GND are the longest pins, SDA and SCL pins medium length and ENABLE the shortest. After the card’s VCC and GND connect with the live backplane, the voltage on VCC starts to rise. At this time, the LTC4304’s precharge circuitry charges the capacitance on the SDA and SCL lines to 1V. Precharged SDA/SCL lines minimize disturbances on the bus when they connect to the backplane. The remainder of the LTC4304’s circuitry is disabled until the supply voltage rises above 2.5V (typical) and the voltage on ENABLE is above 1.4V (typical). Making ENABLE the shortest pin insures that SCL and SDA are firmly seated before a connection is established on the bus. When the VCC supply to the LTC4304 is valid, it assumes that the card is connected to a live backplane and looks for either a stop bit or a bus idle on the backplane side on SDAIN and SCLIN. When one of these conditions is met and SDAOUT and SCLOUT are high, the connection circuitry is activated, connecting the card side bus with the backplane bus. These requirements ensure that the data on the bus is not corrupted when the card is plugged in. READY indicates the status of the connection circuitry and is high when the connection circuitry is active.

Bus Stuck Low Timeout

The LTC4304 monitors SDAOUT and SCLOUT on the card side of the I2C bus. When SDAOUT or SCLOUT is low, an internal timer is started, only to be reset when SDAOUT and SCLOUT are both high. If SDAOUT or SCLOUT do not go high within 30ms, the connection between the inputs and outputs is automatically disconnected, and FAULT asserts low indicating a stuck bus. The LTC4304 also detects a fault if powered up into a stuck bus condition. In either case, the LTC4304 automatically generates up to 16 clock pulses at 8.5kHz on SCLOUT. If SDAOUT and SCLOUT go high, FAULT releases and is pulled high. The LTC4304 then looks for a stop bit or a bus idle before automatically reconnecting. While there is a stuck bus condition, a connection can be forced with a rising edge on ENABLE, even if bus idle conditions are not met.

Capacitance Buffering

The connection circuitry contains a unique patent-pending architecture that provides electrical isolation, isolating the capacitance on the card side bus from the backplane side bus, while maintaining full I2C functionality. This means that the MCU only sees the capacitance of the backplane and the low input capacitance of the LTC4304, <10pF guaranteed by design. The LTC4304 drives the capacitance of the circuitry on the card side. The LTC4304 regulates the voltage on the opposite side from which it is being driven to a slightly higher voltage. This voltage (call it VOS) is a function of VCC, the pull-up resistor, and an internally set constant terms given by the equation:

Equation 1

For example: For a 2.7kΩ pull-up and a VCC of 3.3V,

Equation 2

Rise Time Accelerators

Rise-time accelerators are included on all four SDA and SCL pins. Once activated, the accelerators switch in 3.5mA of current (typical at VCC = 2.7V) into the SDA and SCL lines to make them rise faster. This ensures that rise-time requirements are met and allows the use of larger pull-up resistors to reduce power consumption. When ACC is connected to ground, all four accelerators are ON. When ACC is connected to VCC, all four accelerators are OFF. And when ACC is floating, only the accelerators on SDAOUT and SCLOUT are activated. Accelerators cannot be used on pins where the pull-up voltage is less than VCC. The flexibility of the accelerators control provided by ACC allows the LTC4304 to interface with buses not common with its supply.

Applications

Stuck Bus Automatically Resolved Independent of the MCU

The I2C bus protocol calls for bidirectional communication between devices. A typical example is a microcontroller unit (or MCU) communicating with a slave device. As the slave device’s internal register is read by the MCU, the MCU clocks the slave device to receive each bit of data. A problem occurs when the MCU is out of sync with the slave device—the slave device is waiting for another clock and the MCU thinks it has already sent out enough clocks. If the slave device happens to be holding the data line low, all further communications are prevented and the I2C bus is stuck.

Figure 1 shows a card with a resident LTC4304 that acts as the interface between the devices on the card and the I2C bus, when the card is plugged into the backplane. In normal, plugged-in operation, a connection is established between SDAIN and SDAOUT, and SCLIN and SCLOUT. Internal comparators monitor the SDAOUT and SCLOUT nodes of the circuit. When SDAOUT or SCLOUT is low, an internal timer starts. The timer is only reset when SDAOUT and SCLOUT are both high. If they don’t go high within 30ms, it is determined that the bus is stuck low and the connection between SDAIN and SDAOUT, and SCLIN and SCLOUT is broken, isolating the problem device from the bus. FAULT pulls low indicating a stuck bus. At this time it is assumed that the MCU and the device it is communicating with are out of sync. The MCU sent out all of the clocks necessary for the transaction, but the device is still in the middle of the transaction. The device is waiting for more clocks to finish putting its data on the bus, and the last bit it put on the bus happened to be a low, hence it holds the bus low until it gets more clocks (bus is stuck). Because the connection is broken, the problem device is now isolated from the I2C bus, and the rest of the system is free to resume normal operation.

Figure 1. Typical application of the LTC4304.

After the connection is broken, the LTC4304 automatically generates up to 16 clock pulses at 8.5kHz on SCLOUT, enough clocks to clear the internal register on the problem device. The device could be cleared with one or any number of clocks (up to 16) depending on how the fault occurred. At anytime, if SDAOUT and SCLOUT go high, FAULT is released to go high and the automatic clocking is stopped, and a connection is automatically enabled. When the slave that was stuck sees a START bit after connection, it will abort the stalled communication and reset. The fault is cleared independently of the MCU. If the fault cannot be cleared, the offending circuit remains isolated from the system. Figure 2 shows an example of a stuck bus being resolved with automatic clocking.

Figure 2. Stuck bus resolved with automatic clocking.

Supply Independence and Level Translation

The LTC4304 can be the bridge between a backplane operating at one voltage and a card operating at a different voltage. Figure 3 shows some typical configurations. Notice that VCC, the pull-up voltage on SDAIN and SCLIN and the pull-up on SDAOUT and SCLOUT are independent of each other.

a. VCC is higher than the pull-up voltage on SDAIN and SCLIN.

b. VCC is equal to the output side pull-up voltage, and less than input side pull-up voltage.

c. VCC is greater than the pull-up voltages of both sides.

Figure 3. The LTC4304 can be the bridge between a backplane operating at one voltage and a card operating at a different voltage. Here are three possible scenarios and appropriate configurations.

The rise time accelerators must be disabled when the bus pull-up voltage is lower than VCC. Figure 3a shows a situation where the VCC is higher than the pull-up voltage on SDAIN and SCLIN. In this case ACC must be floating, disabling the rise time accelerators on the inputs only. In Figure 3b, VCC is equal to the output side pull-up voltage, and less than input side pull-up voltage. ACC is connected to GND to enable all four rise time accelerators. Finally, in Figure 3c, VCC is greater than the pull-up voltages of both sides. ACC is connected to VCC to disable all four accelerators.

Conclusion

The LTC4304 is a multifunctional device with an impressive number of features designed to increase the reliability of an I2C bus. The flexible architecture allows the LTC4304 to be configured into almost any system. The LTC4304 isolates and resolves stuck buses independently of the MCU. Capacitance buffering, level translation, Hot Swap features and ±15kV human body ESD protection make the LTC4304 an ideal solution for any I2C application.

The LTC4304 is offered in small 10 pin MSOP and DFN (3mm × 3mm) packages.

A feature-reduced version of the LTC4304 is also available. The LTC4303 provides all of the functionality of the LTC4304 with the exception of the FAULT output flag and ACC control pin. The LTC4303 is a drop in replacement for the LTC4300A-1 and its rise time accelerators are permanently enabled.

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George Humphrey