When a board is plugged into the live backplane of a host system (hot swapped), the bulk bypass capacitors of the board can draw large inrush currents as they charge. These transient currents can damage connectors or create glitches on the backplane, potentially causing other boards in the system to inadvertently reset. To prevent such large inrush currents, the bulk bypass capacitors on the plug-in board must be isolated during the Hot Swap sequence.
The LTC4240 provides a controlled on-off switch for four hot swappable board power supply voltages, allowing the board to be safely inserted or removed from a live CompactPCI (CPCI) slot without disturbing the system power supplies. The LTC4240 includes an I2C-compatible interface that allows software control and monitoring of device function and power supply status.
Hot Swap features include:
- PRECHARGE output for biasing I/O connector pins during board insertion and extraction
- Circuit breakers on all four supplies with 35μs overcurrent glitch filters
- Foldback current limit to reduce power dissipation while charging large capacitive loads and during short circuit conditions
- Supports backplanes with and without bypass capacitors
I2C read and write functions include:
- Under a fault condition, determine which supply created the fault
- Read the maximum allowed board power consumption: PRSNT1#, PRSNT2#
- Cycle board power, reset the board after a fault condition
- Ignore faults on the +12V and –12V supplies
Typical Hot Swap Application
Figure 1 shows a CPCI Hot Swap application. Transistors Q1 and Q2 isolate 3.3V and 5V backplane power supplies from the plug-in board’s bulk capacitance. The currents through Q1 and Q2 are sensed by R1 and R2. Resistors R3 and R4 prevent high frequency oscillations in Q1 and Q2. R5 and C1 stabilize the 3.3V and 5V current limit loop. During a fault condition, R5 also serves to isolate C1 from the fast internal pull down resistor. Capacitors C7 and C8 are 0.01μF, per the CPCI Hot Swap specification. On-chip power transistors isolate the –12V and +12V supplies. Transistor Q3 and its associated components form the precharge circuit.
CompactPCI Connection Pin Sequence
The staggered lengths of the CPCI male connector pins ensure that all power supplies are physically connected before back-end power is allowed to ramp (BD_SEL# asserted low). The long pins, which include 5V, 3.3V, V(I/O) and GND, mate first. The short pins, which includes BD_SEL# (OFF/ON), mate last. The 3.3V and 5V long pins must be connected to the LTC4240 in order for the 1V PRECHARGE voltage to be available during early power. The following is a typical hot-plug sequence:
- ESD clips make contact.
- Long power and ground pins make contact and the 1V PRECHARGE becomes valid. Power is applied to the pull-up resistors connected to FAULT, PWRGD, and OFF/ON pins. The status LED is lit, indicating that the plug-in board is in the process of being connected (LOCAL_PCI_RST# is asserted). All power switches are off.
- Medium length pins make contact. There are six 5V and eight 3.3V medium length pins, bringing the 5V total to eight pins and the 3.3V total to ten pins. The CPCI specification limits the DC current to 1A/pin. The I2C latch is initialized to allow seamless CPCI Hot Swap operation.
The +12V and –12V supply pins make contact at this stage. Zener clamps Z1 and Z2 plus shunt RC snubbers R13-C4 and R14-C5 help protect the +12V and –12V supply inputs, respectively, from large transient voltages during hot insertion and short circuit conditions. The signal pins also connect at this point. This includes the HEALTHY# signal connecting to the PWRGD pin, and the PCI_RST# signal connecting to the RESETIN pin.
- Short pins make contact last. BD_SEL# signal connects to the OFF/ON pin, thus starting the electrical connection process. If the BD_SEL# signal is grounded on the backplane, the electrical connection process begins immediately. The electrical connection process can be interrupted at any time via the I2C serial interface.
Figure 2 shows a typical power-up timing sequence. The connection sequence is triggered by a high to low transition on the BD_SEL# signal or by a power cycling executed by the I2C interface. A 65μA current source charges the gate nodes of the external power transistors. The power-up voltage rate of the 3VOUT and 5VOUT is approximately given by: dV/dt = 65μA/C1 or as determined by the current limit and the load capacitances.
Concurrently, an 11.5μA current source charges up the TIMER pin capacitance. Current limit faults are ignored until the voltage at the TIMER pin reaches 5.5V. Once all output supply voltages have crossed their power good thresholds, the HEALTHY# signal is pulled low (green LED turns on) and LOCAL_PCI_RST# is free to follow PCI_RST# and bit C3 of the I2C command latch.
Controlled Turn-Off Allows Safe Extraction
Figure 3 shows a typical power-down timing sequence. When either BD_SEL# or bit C2 of the I2C command latch is set high, a 200μA current source discharges the capacitance on the gates of the external FETs. The internal +12V and –12V power switches also turn off. The four power switches are turned off slowly to avoid glitching the power supplies. Internal resistors discharge the output load capacitors. Once the power-down sequence is complete, the status LED lights up and the CPCI card can then be safely removed from the slot.
Disconnecting PRECHARGE Resistors
Universal Hot Swap and 3.3V signaling boards use a 50k, or larger, resistor to precharge the I/O lines. Since leakage currents at the I/O lines can be as high as 10μA, a 10k biasing resistor is allowed, but must be disconnected during normal operation. Figure 4 shows an application circuit that connects the PRECHARGE voltage to the I/O lines during insertion, but disconnects the resistors once the BD_SEL# pin makes contact.
Control and Monitor Card Power with I2C Interface
The LTC4240 incorporates an I2C compatible 2-wire (SCL, SDA) interface that allows the user to easily query and control the status of the LTC4240. A single analog pin selects 1 of 32 allowed addresses. The LTC4240 supports send byte and receive byte commands. Figure 5 and Table 1 depict the timing and bit definition of the send byte command. Figure 6 schematically outlines some of the command bit functions. Figure 7 shows the timing of the receive byte command. Tables 2 and 3 define the data byte. If a fault occurs, the FAULTCODE bits can be used to determine which supply generated the fault.
|C5||Ignore VEEOUT Faults||Does not Ignore VEEOUT Faults|
|C4||Ignore 12VOUT Faults||Does not Ignore 12VOUT Faults|
|C3||Sets RESETOUT Low||Does not Set RESETOUT Low|
|C2||Turns off all switches
Overrides OFF/ON Pin
|Does not turn off all switches
Does not override OFF/ON pin
|C1||Turns on LED||Does not turn on LED|
|S7||Logic State of the PRSNT2# Pin|
|S6||Logic State of the PRSNT1# Pin|
|S5||Logic State of the PWRGD Pin|
|S4||Logic State of the RESETOUT Pin|
|S3||Logic State of the RESETIN Pin|
|S2||FAULTCODE1 (See Table 3)|
|S1||FAULTCODE0 (See Table 3)|
|S0||Logic State of the FAULT pin|
|FAULTCODE0||FAULTCODE1||FAULT||Supply Causing Fault|
The LTC4240 provides a comprehensive solution to CompactPCI Hot Swap applications. An integrated I2C-compatible interface allows software control and monitoring of device function and power supply status. The LTC4240 control functions allow the plug-in board to be safely inserted or removed from a live CompactPCI slot without disturbing the system power supplies or I/O lines.