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Figure 1

   

Key Takeaways Tame the right-half-plane (RHP) zero to unlock stable loop bandwidth. Inductance selection sets the RHP zero frequency, which directly limits your inverting buck-boost converter's achievable crossover. Follow step-by-step Type-II compensator equations verified by LTspice® simulation. Target crossover at 0.1× to 0.3× of the RHP zero frequency for adequate gain margin and transient response.

Abstract

This article describes a systematic method for designing a Type-II (two-pole, one-zero) voltage-mode compensator for monolithic inverting buck-boost (IBB) converters, including standard buck regulators configured for negative output operation. The article begins with power-stage design considerations for a given set of electrical requirements and derives the small-signal control-to-output transfer function for peak current-mode control. Based on this model, a practical compensator is synthesized to achieve adequate loop stability and transient response. Design equations are summarized in a step-by-step procedure, and the resulting loop characteristics are verified using LTspice® simulations. This article serves as a practical reference for voltage-loop compensation of IBB converters.

Introduction

Many electronic systems require one or more negative supply rails, typically implemented alongside corresponding positive rails to form symmetrical power supplies. These negative voltages are essential for proper biasing, signal swing, and device operation in various applications, such as:

• Gate driver circuits for power electronics in electric vehicles, enabling efficient switching of wide-bandgap devices like gallium nitride (GaN) FETs and insulated-gate bipolar transistors (IGBTs) in chargers and traction inverters.
• Precision analog front ends, including high-resolution analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and rail-to-rail operational amplifiers, where negative rails allow full dynamic range and linearity in industrial and medical instrumentation.
• LCD biasing for consumer electronics, where negative voltages are required for proper pixel control and contrast adjustment.
• Photodiode biasing, including avalanche photodiodes, to achieve high-speed response and low noise in optical sensing systems.
• Medical imaging equipment, such as X-ray generators, which rely on negative voltages for detector bias and signal conditioning.

Negative rails are typically generated using an inverting buckboost (IBB) topology. In monolithic implementations, this can be realized in two common ways.

1. Dedicated IBB regulator ICs.
2. Standard buck regulators reconfigured for inverting operation by rerouting the power stage.

Figure 1 shows a dedicated IBB solution, while Figure 2 illustrates a buck regulator configured as an IBB.

This article analyzes both approaches using a practical design example. The small-signal power-stage transfer function is derived for peak current-mode control operating in continuous conduction mode (CCM). Using this model, a voltage-loop compensator is designed to achieve a target bandwidth and phase margin. For devices with internal compensation, designers should follow the recommendations provided in the respective data sheets.

Table 1. Design Requirements

Parameter	Value
Input voltage, VIN	5V
Output voltage, VOUT	–5V
Load current, IOUT	1A
Switching frequency, fSW	3.3MHz
Efficiency, η	90%
Upper feedback resistor, Ru	454kΩ
Lower feedback resistor, Rb	49.9kΩ
Load resistor, R	5Ω
Power block transconductance, Gm	6S
Transconductance of error amplifier, gm	12ms

• Continuous conduction mode (CCM)
• Peak current-mode control
• Small-signal linear operation around the steady-state operating point
• Absolute value of V_OUT is used in duty-cycle and power calculations
• The analysis assumes a peak current-mode controlled converter with internal slope compensation and a high-bandwidth inner current loop, allowing the outer voltage loop to be modeled using a Type-II compensator.

Design of Power Stage

The steps for designing the power stage are as follows:

1. For an IBB converter, the ideal duty cycle is calculated using the magnitude of the output voltage:

$$\begin{array}{cc}D=\frac{\left|V_{\mathrm{OUT}}\right|}{V_{\mathrm{IN}}+\left|V_{\mathrm{OUT}}\right|}& \text{(1)}\end{array}$$

2. The average current through the inductor is determined as:

$$\begin{array}{cc}{I}_L=I_{\mathrm{OUT}}(1+\frac{\left|V_{\mathrm{OUT}}\right|}{V_{\mathrm{IN}}\times \eta })\text{\hspace{0.17em}A}& \text{(2)}\end{array}$$

3. The peak inductor current can be calculated using the following expression, assuming an AC ripple current of 30% of the average inductor current (represented by 0.3):

$$\begin{array}{cc}{I}_{\mathrm{Lpeak}}=I_L+\frac{\Delta I_L}{2}\text{\hspace{0.17em}A}& \text{(3)}\end{array}$$

where:

$$\begin{array}{cc}\Delta I_L=0.3\times I_L\text{\hspace{0.17em}A}& \text{(4)}\end{array}$$

4. The inductor to be selected should have an I rms rating greater than I_L, and I_SAT rating greater than I_L,peak. The inductance required is determined as:

$$\begin{array}{cc}L=\frac{V_{\mathrm{IN}}\times D}{\Delta I_L\times f_{\mathrm{sw}}}\text{\hspace{0.17em}H}& \text{(5)}\end{array}$$

For buck converter ICs configured in IBB mode with a duty cycle greater than 50%, the selected inductance must exceed the minimum required inductance L_min, as specified in the respective product data sheet. An example formula from the LT8624S is:

$$\begin{array}{cc}{L}_{\min }=\frac{V_{\mathrm{IN}}\times (2\times D-1)}{2.5\times f_{\mathrm{sw}}}\text{\hspace{0.17em}H}& \text{(6)}\end{array}$$

When applying the L_min formula for the IBB configuration, replace V_IN with V_IN + |V_OUT|, and use the duty cycle D, calculated in Step 1. The resultant formula is:

$$\begin{array}{cc}{L}_{\mathrm{min\_IBB}}=\frac{(V_{\mathrm{IN}}+|V_{\mathrm{OUT}}|)\times (2\times D-1)}{2.5\times f_{\mathrm{sw}}}\text{\hspace{0.17em}H}& \text{(7)}\end{array}$$

5. The right-half-plane (RHP) zero is determined as per the following expression:

$$\begin{array}{cc}{f}_{\mathrm{rhp}}=\frac{\left|V_{\mathrm{OUT}}\right|\times {(1-D)}^2}{2\times \pi \times L\times D\times I_{\mathrm{OUT}}}\text{\hspace{0.17em}Hz}& \text{(8)}\end{array}$$

Since V_out is negative, the absolute value of the same is considered.

6. The target crossover frequency, f_cr, is at a range of 0.1 × f_rhp to 0.3 × f_rhp. Selecting f_cr = 0.3 × f_rhp Hz.

7. Considering a step load current, I_STEP = 0.5 × I_OUT for a 3% V_OUT ripple (ΔV_OUT = 0.03 × V_OUT), the output capacitance is calculated as:

$$\begin{array}{cc}{C}_{\mathrm{OUT}}=\frac{I_{\mathrm{STEP}}}{2\times \pi \times f_c\times \Delta V_{\mathrm{OUT}}}\text{\hspace{0.17em}F}& \text{(9)}\end{array}$$

Note the C_OUT value calculated is derated to V_OUT.

8. The slope compensation, S_E, is determined from Equation 7, which is the denominator, that is 2.5 × f_SW A/s.

9. The current sense resistance, R_i, can be approximated by:

$$\begin{array}{cc}{R}_i=\frac{1}{G_m}\text{\hspace{0.17em}Ω}& \text{(10)}\end{array}$$

Generally, the slope and the current sense information are not made directly available in the data sheet.

10. Evaluate the inductor current slope S_N as:

$$\begin{array}{cc}{S}_N=\frac{V_{\mathrm{IN}}}{L}\text{\hspace{0.17em}A/s}& \text{(11)}\end{array}$$

11. The power stage output to control transfer function thus obtained is:

$$\begin{array}{cc}{G}_{\mathrm{VCI}}(s)=K_{\mathrm{VCI}}\times \frac{(1-\frac{S}{{\omega }_{\mathrm{rhp}}})\times (1+\frac{S}{{\omega }_{\mathrm{esr}}})}{(1+\frac{S}{{\omega }_{\mathrm{pl}}})\times (1+\frac{S}{Q_p\times {\omega }_n}+\frac{S^2}{{{\omega }_n}^2})}& \text{(12)}\end{array}$$

where:

$$\begin{array}{cc}{K}_{\mathrm{VCI}}=\left(\frac{(1-D)\times R}{R_I}\right)\times \frac{1}{1+\left(\frac{{(1-D)}^3\times R\times T_S\times (m_c-0.5)}{(1+D)\times L}\right)}& \text{(13)}\end{array}$$ $$\begin{array}{cc}{\omega }_{\mathrm{rhp}}=2\times \pi \times f_{\mathrm{RHP}}\text{\hspace{0.17em}rad/s}& \text{(14)}\end{array}$$ $$\begin{array}{cc}{\omega }_{\mathrm{esr}}=\frac{1}{R_c\times C_{\mathrm{OUT}}}\text{\hspace{0.17em}rad/s}& \text{(15)}\end{array}$$

R_c is the ESR of the output capacitor in Ω

$$\begin{array}{cc}{\omega }_{\mathrm{pl}}=\frac{1+D}{R\times C_{\mathrm{OUT}}}+\frac{T_S\times {(1-D)}^3\times (m_c-0.5)}{L\times C_{\mathrm{OUT}}}\text{\hspace{0.17em}rad/s}& \text{(16)}\end{array}$$ $$\begin{array}{cc}{Q}_p=\frac{1}{\pi \times (m_c\times (1-D)-0.5)}& \text{(17)}\end{array}$$ $$\begin{array}{cc}{\omega }_n=\pi \times f_{\mathrm{sw}}\text{\hspace{0.17em}rad/s}& \text{(18)}\end{array}$$ $$\begin{array}{cc}{m}_c=1+\frac{S_E}{S_N}& \text{(19)}\end{array}$$

The parameters calculated and finalized as per the design considerations are shown in Table 2.

Table 2. Power Stage Parameters

D	0.5	COUT (F)	11.79µ
L (H)	2.7µ	KVCI	12.18
frhp (Hz)	147.365k	ωrhp (rad/s)	925.925k
fcr (Hz)	45k	ωpl (rad/s)	31.343k

Design of External Compensator 

Figure 3 represents a two-pole, one-zero voltage Type-II voltage-loop compensator. The transfer function of the same is:

$$\begin{array}{cc}\frac{K_v}{s}\times \frac{(1+\frac{s}{{\omega }_{\mathrm{zc}}})}{(1+\frac{s}{{\omega }_{\mathrm{pc}}})}& \text{(20)}\end{array}$$

The combination of the control to output transfer function and the output voltage feedback provides insight into designing the compensator transfer function. The guidelines below are followed for the same:

1. The additional gain required for the loop transfer function to obtain the required bandwidth:

$$\begin{array}{cc}{G}_{\mathrm{req}}=\frac{{\omega }_{\mathrm{cr}}}{H\times K_{\mathrm{VCI}}\times {\omega }_{\mathrm{pl}}}& \text{(21)}\end{array}$$

where:

$$\begin{array}{cc}H=\frac{R_b}{R_u+R_b}& \text{(22)}\end{array}$$ $$\begin{array}{cc}{\omega }_{\mathrm{cr}}=2\times \pi \times f_{\mathrm{cr}}\text{\hspace{0.17em}rad/s}& \text{(23)}\end{array}$$

2. The phase shift of the power stage transfer function as:

$$\begin{array}{ll}\mathrm{PS}=-{\tan }^{-1}\frac{{\omega }_{\mathrm{cr}}}{{\omega }_{\mathrm{rhp}}}+{\tan }^{-1}\frac{{\omega }_{\mathrm{cr}}}{{\omega }_{\mathrm{esr}}}-{\tan }^{-1}\frac{{\omega }_{\mathrm{cr}}}{{\omega }_{\mathrm{pl}}}-& \text{(24)}\\ {\tan }^{-1}\frac{{\omega }_{\mathrm{cr}}}{Q_p\times {\omega }_n}\text{\hspace{0.17em}deg,}({\omega }_n\gg {\omega }_{\mathrm{cr}})& \end{array}$$

3. For a buck-boost converter, a good phase margin (PM) is above 45°. Selecting a PM of 60°, the phase boost required is:

$$\begin{array}{cc}\mathrm{Boost}=\mathrm{PM}-\mathrm{PS}-90°& \text{(25)}\end{array}$$

4. The factor k is evaluated as:

$$\begin{array}{cc}k=\tan (\frac{\mathrm{Boost}}{2}+45)& \text{(26)}\end{array}$$

5. The compensator pole ω_pc and compensator zero ω_zc are obtained as:

$$\begin{array}{cc}{\omega }_{\mathrm{pc}}={\omega }_{\mathrm{cr}}\times k\text{\hspace{0.17em}rads/s}& \text{(27)}\end{array}$$ $$\begin{array}{cc}{\omega }_{\mathrm{zc}}=\frac{{\omega }_{\mathrm{cr}}}{k}\text{\hspace{0.17em}rad/s}& \text{(28)}\end{array}$$

6. The integrator gain is obtained as:

$$\begin{array}{cc}{K}_v=G_{\mathrm{req}}\times {\omega }_{\mathrm{zc}}& \text{(29)}\end{array}$$

7. The components for the above compensator are designed as:

$$\begin{array}{cc}{R}_z=\frac{G_{\mathrm{req}}}{g_m}\text{\hspace{0.17em}Ω}& \text{(30)}\end{array}$$ $$\begin{array}{cc}{C}_z=\frac{g_m}{K_v}\text{\hspace{0.17em}F}& \text{(31)}\end{array}$$ $$\begin{array}{cc}{C}_p=\frac{1}{R_z\times {\omega }_{\mathrm{pc}}}\text{\hspace{0.17em}F,}(C_p\ll C_z)& \text{(32)}\end{array}$$

Table 3 shows the compensator designed for the power stage.

Table 3. Compensator Parameters

ωpc (rad/s)	3.696M	Cp (F)	433.954p
ωzc (rad/s)	21.625k	Cz (F)	74.184n
Kv (s/rad)	161.758k	Rz (Ω)	623.345

LTspice® Simulation and Observations

The simulation of the IBB stage, configured with the parameters derived in Table 3, is shown in Figure 4.

At a crossover frequency of 46.269kHz, the loop exhibits a gain margin (GM) of 8.90dB and a PM of 59.07°, GM is expected to be greater than 10dB. This can be improved by tuning the compensator pole. In this design, transient response was prioritized over gain margin, resulting in a measured GM of 8.9dB, which is acceptable for the intended operating range.

During the load step, the transient waveform exhibits an output-voltage excursion of roughly 2.88%, indicating the converter’s dynamic response characteristics.

Design Sensitivity

From the above analysis, it is evident that the selection of the inductor, L, directly influences the location of the RHP zero and, consequently, limits the maximum achievable crossover frequency of the IBB converter. The choice of output capacitance, C_OUT, not only determines the output-voltage excursion during load transients, but together with its equivalent series resistance (ESR) and the inductor, L, also shapes the dominant power stage pole. These parameters collectively dictate the required loop gain and phase boost during compensator design, and therefore ultimately determine the resulting phase margin of the system.

Final Design Checklist

The checklist below outlines the essential design requirements:

• High RHP zero for adequate bandwidth (via inductance selection).
• PM > 45°.
• GM ≥ 10dB is recommended; however, slightly lower GM may be acceptable when transient performance is prioritized.
• Output voltage deviation ≤ 3% during load transients.

Conclusion

This article presents a structured and repeatable approach for compensator design in IBB converters. By deriving the small-signal power stage model and explicitly accounting for the RHP zero, designers can select an appropriate loop bandwidth and compensation network. LTspice simulations confirm that the proposed method achieves stable operation and fast transient response, making it suitable for a wide range of negative-rail generation applications.

References

• Basso, Christophe P. Switch-Mode Power Supplies, Second Edition. McGraw-Hill Professional, February 2008.
• Lamp, Erik. “Fast-Transient Negative Voltage Rail for Noise-Sensitive Applications.” Analog Devices, Inc., July 2024.
• Lamp, Erik and Randyco Prasetyo. “Generating Negative Voltages from a Positive Voltage Supply: Market Requirements and Solutions.” Analog Devices, Inc., September 2024.
• Mitra, Dipankar. “How to Use the MAX17501 and MAX17502 for Negative Output Voltage Applications.” Analog Devices, Inc., April 2014.
• Nelson, Carl. “AN19—LT1070 Design Manual.” Linear Technology, June 1986.
• Ridley, Raymond B. “A New Small-Signal Model for Current-Mode Control.” Ridley Engineering, Inc., 1999.

著者について

Rakshith Prasad Shashibhushan

Rakshith Shashibhushan is a product applications senior engineer in the High Performance Power Group at Analog Devices. He received his master’s degree in power electronics and drives from the National Institute of