×

Figure 1

   

Key Takeaways Low-capacitor ESR can cause dangerous resonant peaking in LC input filters. Apply the Middlebrook criterion and add damping to keep filter output impedance below converter input impedance for stability. A two-stage LC filter achieves over 100dB attenuation with smaller components than a single stage. This margin ensures compliance even after capacitor derating from bias voltage and temperature effects.

Abstract

A switching DC-to-DC converter draws a pulsating input current with rich harmonic content due to its switching action. These high-frequency (HF) current components can flow back into the input power leads and couple into other parts of the system, degrading overall power bus quality. From an electromagnetic compatibility (EMC) perspective, the converter acts as a noise source. One solution is to place an input filter between the converter and the power bus to prevent switching noise from being conducted back to the source. A poorly designed input filter may fail to sufficiently attenuate the HF components and can also cause output oscillations or converter failure. This article presents the design considerations, calculations, and simulations needed to implement an LC differential-mode (DM) input filter using LTspice. It focuses on DM filtering; in practice, common-mode (CM) filtering is often also required for full compliance.

Introduction

Switching regulators are widely used because they provide high-efficiency power conversion, but their switching action also makes them a source of conducted noise. In many systems, especially those that include sensitive analog, RF, or communication circuits, this noise must be controlled before it propagates through the input power bus. An input filter is often the first line of defense, but it cannot be treated as a simple add-on component. Its resonance, damping, impedance interaction with the converter, and startup behavior can all affect system performance.

This article walks through the practical design of a differential-mode (DM) input filter for a DC-to-DC converter. It first reviews the basic behavior of an LC filter, including attenuation slope, capacitor equivalent series resistance (ESR), and resonant peaking. It then shows how damping can be added to improve stability, how an undamped filter can create startup overvoltage or output oscillation, and how LTspice can be used to estimate conducted-emissions attenuation and compare single-stage and two-stage filter solutions.

Differential-Mode LC Filter Behavior

An LC filter is a double-pole filter, and its resonant frequency is given by:

Each pole contributes –20dB/dec of attenuation, for a total of –40dB/dec. The ESR of the filter capacitor introduces a zero, which contributes +20dB/dec to the slope. The zero frequency is given by:

Figure 1 shows an example of a typical LC filter. L1 and C2 form the filter, C1 is the decoupling capacitor for V1, and Cin represents the input capacitance of the DC-to-DC converter. A switching DC-to-DC converter draws a pulsating input current with rich harmonic content due to its switching action. The filter must attenuate this input current across the relevant frequency range so that it does not flow back into the source and pollute the bus voltage that powers other sensitive electronics. As frequency increases, the reactance of C2 decreases while the reactance of L1 increases, causing the current harmonics to be diverted to ground.

It is desirable for the filter inductor to have neither excessively high inductance nor high direct current resistance (DCR). A large inductance slows the response to load transients, and because the inductor is in series with the input, its DCR should be minimized to reduce voltage drop and power loss. The trade-off is that, for the same f₀, reducing the inductance requires increasing the capacitance. The capacitor ESR also affects the total attenuation at the frequency of interest.

Figure 1 shows an LTspice schematic in which the ESR is stepped between two values, 1mΩ and 100mΩ. The value of f0 remains fixed at 33.4kHz because it is not determined by capacitor ESR, but the ESR zero, f_ESR, shifts from 7.23MHz (1mΩ) to 72.34kHz (100mΩ). Figure 2 shows the simulation results for this circuit. If the DC-to-DC converter switches at 1MHz, the difference in attenuation is 22.7dB. The ESR zero limits the achievable high-frequency attenuation by reducing the filter slope from –40dB/ dec to –20dB/dec.

Designers usually prefer components with low DCR and low ESR, and this is generally the right approach. However, because an LC filter is a type of resonant RLC network, very low ESR can produce significant peaking at f₀. This means that the output impedance of the input filter reaches a high value, making the design more susceptible to instability. According to the Middlebrook criterion, the output impedance of the input filter must remain lower than the input impedance of the converter to avoid instability. Therefore, this peak must be damped. This peaking is related to the quality factor, which is given by:

If f_ESR ≫ f₀, the filter will exhibit a high Q and significant peaking, although it will retain the –40dB/dec slope. If f_ESR ≫ f₀, then Q ≈ 1, which results in a damped response. This can be achieved by adding a series RC branch in parallel with the filter capacitor. For Q ≈ 1, the damping resistor value is:

The damping capacitor is typically chosen to be 3× to 10× the filter capacitor value.

Undamped and Damped LC Filter Design Example

Figure 3 shows the difference between an undamped and a damped filter when the filter capacitor has a low ESR of 1mΩ. C5 was chosen to be 4.5× the value of C4, and R1 was calculated to be 0.213Ω, so a 0.2Ω resistor was used. Figure 4 shows the simulation results, demonstrating no peaking and similar attenuation of –58dB at 1MHz.

 

When an undamped filter is connected to the input of a DC-to-DC converter, two design problems may arise.

1. The IC may fail at startup:
   
   At startup, the input voltage can ring to nearly twice V_IN. If the design converts 12V to 5V and the IC has an absolute maximum input rating of 42V, this startup overvoltage is unlikely to damage the part. However, in a 28V to 5V design, the ringing can exceed the absolute maximum input rating, potentially causing IC failure.
2. The output may oscillate:
   
   The LC filter has a natural tendency to oscillate at f₀, and the pulsating input current can excite this resonance continuously. Figure 5 shows the built-in LTspice schematic for the LT8609S. An input filter and additional input capacitors were added to replicate an undamped filter design. The filter resonance, f₀, is determined by L2 and the total capacitance, CT = C7 + C8 + C9, and is calculated as:
   
   The results are shown in Figure 6, where the output voltage appears to oscillate at the resonant frequency of the filter. Probing the after_filter net reveals the cause: the input voltage is oscillating. In addition, the peak voltage reaches 46.6V, which exceeds the 42V absolute maximum input rating of the LT8609.

 

Design Example in LTspice

In this example, a radio receiver requires conversion from 15V to 5V at 3A load current. The switching frequency is 1MHz, and the design must comply with MIL-STD-461G. The LT8624S, a Silent Switcher^® generation 3 device, was selected for its low noise and low electromagnetic interference (EMI) performance. Using the data sheet and LTpowerCAD, the component values for this design were calculated and are shown in Figure 7.

 

MIL-STD-461G provides conducted emissions limits for power leads in CE101 from 30Hz to 10kHz and in CE102 from 10kHz to 10MHz. The limits are given in dBμV and are intended for use with a line impedance stabilization network (LISN), which is placed between the power source and the equipment under test (EUT). The LISN provides a known impedance, typically about 50Ω, and converts the conducted current emitted by the EUT into a measurable voltage at its output. An LTspice LISN circuit can be found in the article “How to Get the Best Results Using LTspicefor EMC Simulation—Part 1.” Figure 8 shows the CE102 limits graph. For systems below 28V, the CE102 basic curve gives a flat limit of approximately 60dBμV above about 1MHz. After the simulation is complete, plot the current through V1 by hovering the cursor over the voltage source; the cursor changes to a current probe, after which you can left-click. Once I(V1) is displayed, right-click in the waveform viewer and select View → FFT. A window will open that allows waveform selection for the fast fourier transform (FFT) display. Select I(V1) and click OK. The FFT of I(V1) is then displayed, with magnitude shown in dB on the left axis. To convert the magnitude to a linear scale, hover over the left vertical axis until the cursor changes to a ruler, then right-click to open the Left Vertical Axis – Magnitude window. Change the radio button from Decibel to Linear and click OK. The input-current magnitude is then shown on a linear scale. Figure 9 shows that the magnitude of I(V1) is approximately 657mA. To convert this current to voltage, use the LISN input impedance of approximately 50Ω:

To convert 32.85V to dBμV:

The required filter attenuation is 150dB – 60dB = 90dB. Another way to calculate this is to note that 60dBμV = 1mV. This means that

Dividing the simulated 657mA by 20μA gives 32,800, and 20log (32800) = 90.31dB.

 

The next step is to determine the filter resonant frequency required to achieve –90dB attenuation at 1MHz. The attenuation of an LC filter is given by:

In this process, the inductor is chosen first, and the filter equation is then used to solve for C. An attenuation target of 90dB is very high for a single LC filter and makes it impractical to choose suitable components while maintaining fast transient response. For example, if a 4.7μH inductor is selected:

To damp the filter, at least 170μF × 3 = 510μF is required, which is excessive. One option is to increase the inductor value and use only a single LC filter. This would reduce the number of components, but at the expense of size, cost, and transient response. A more practical solution is to use a two-stage LC filter, which forms a fourth-order filter with a slope of –80dB/dec before reaching f_ESR. The steeper slope allows f0 to be placed 10× higher in frequency while still meeting the attenuation target. For comparison, with f₀ = 56.2kHz, a 33μH inductor is selected for the single-stage LC filter, whereas a 1μH inductor is used for the two-stage LC filter.

Figure 10 shows the two filters, and Figure 11 presents the simulation results. The single-stage filter barely reaches –90dB and can do so only if the capacitor ESR is 2mΩ or less, indicating that the ESR zero is already affecting the slope. The 33μH inductor is too large for f_SW = 1MHz and is not well suited to fast transient response. In contrast, the two-stage LC filter provides more than –100dB of attenuation using smaller-value components. This additional attenuation margin increases confidence that the 90dB target will still be met even after capacitor derating due to bias voltage and temperature.

 

 

Conclusion

In summary, this article has shown how an input filter for a switching regulator must be designed as both an EMI filter and a stable power interface to the converter. A simple LC filter can provide strong differential-mode attenuation, but capacitor ESR, resonant peaking, startup behavior, and interaction with the converter input impedance must all be considered to avoid instability or overvoltage stress. LTspice makes it possible to estimate required attenuation from conducted emissions limits, compare single-stage and two-stage solutions, and verify the benefits of damping before hardware is built. As practical design guidance, start from the emissions target and the relevant frequency range, choose the smallest inductance that still provides the required attenuation, use low-DCR components while adding intentional damping when needed, check for resonant peaking and startup overshoot, account for capacitor derating and ESR variation, and validate the final design with both frequency-domain and time-domain simulations before moving to lab measurements with a LISN.

著者について

Rani Feldman

Rani Feldmanは、シニア・フィールド・アプリケーション・エンジニアとして2017年にアナログ・デバイセズに入社しました。それ以前はリニア・テクノロジー（現在はアナログ・デバイセズの一部門）に3年間勤務していました。イスラエルのアフェカ大学で電子工学の学士号、同じくイスラエルのホロン工科大学で経営管理学の修士号を取得しています。