Smart GaN Buck Controller Designs—Part 1: Considerations and Measurements

質問:

How can the physical parasitic elements introduced by probes and the placement of connectors like MMCX affect the accuracy of dead time and overshoot waveform measurements in GaN-based synchronous buck converters, and what are the recommended techniques to mitigate these issues?

回答:

Parasitic reactance elements introduced by probe connections can distort the waveform, leading to incorrect information about the gate signals. The placement of connectors like MMCX can introduce physical board space constraints or additional trace inductance and resistance, which can further affect measurement accuracy. Minor adjustments to the layout can significantly impact the measured overshoot, making it essential to balance these trade-offs carefully. To mitigate these issues, specialized probes and connectors are recommended, such as the MMCX style connector or header pins that adapt to MMCX probe tips. Differential probes such as the Tektronix TIVP or TICP can provide the necessary isolation for top gate measurements and are often used with the MMCX connector. Custom pigtail application probing techniques, with a properly chosen return path for the bottom gate and switch nodes, and differential probes for measuring top gate waveforms are also suggested.

Introduction

The introduction of wide bandgap FET devices such as gallium nitride (GaN) in power conversion offers higher energy density, faster switching, and lower losses due to their dramatically lower gate capacitance (Cg). GaN FETs, however, have very tight V_GS limits and do not have a body diode. Because of this, the reverse conduction losses are much higher with longer dead times if the gate slew rate is lowered to avoid gate ringing. But they are still just as subject to the deleterious effects of shoot-through. To take full advantage of these devices, dead time must therefore be optimized. Consider the typical application in Figure 1. This is a 15 V to 36 V_IN, 12 V/15 A step-down converter featuring the LTC7891. It is designed specifically for driving GaN devices, and we will examine how to accurately measure dead time and overshoot while optimizing the gate resistor using this application circuit.

Switching Operation Considerations

The switching network for the buck converter with smart near-zero dead time is comprised of the controller that drives control switch Q1 top gate (TG) and a synchronous switch Q2 bottom gate (BG). The top gate is driven with separate pullup/pull-down resistors (TGUP, TGDN) and the bottom gate is driven with separate pull-up/pull-down resistors (BGUP, BGDN). Switching currents during each switch cycle are averaged with the output filter network L1 and C_OUT to produce a regulated output voltage.

An ideal converter would have lossless switches that turned on and off instantly in perfect unison. However, while GaN FETs are capable of being turned on and off more quickly than other technologies due to their low capacitance, there are delays between the controller commanding a switch on, and that switch reaching a fully on state. The same holds true for turning the switch off. Because of this delay, there are transition losses that become an important part of the total losses of switching operation. These losses translate into switch heat, which hurts efficiency and ultimately imposes thermal limits of operation for the FET. But how does one practically work with these limits imposed by nonideal switches?

If both switches are fully on—even for a fraction of a second—low R_DS(ON) means a short circuit from V_IN to GND, and catastrophic switch failure is the result. If both switches are partially on, high drain currents cause instantaneous high temperature rises that stress the switches and reduce their lifetime. This condition is known as shoot-through (Figure 2). The initial switching has roughly 8 ns of dead time and the switch current has a normal di/dt associated with switching to input current, then ramping as the inductor charges. The next transition has symmetric rising and falling edges, allowing both transistors to be partially on and resulting in a sharp spike of drain current that is still below I(DS)_MAX. The final transition allows 2 ns of on-time overlap and the drain current spikes well beyond the rated FET drain current.

To avoid this, controllers turn one switch off and then delay the turn-on of the other, which is a period known as dead time. This prevents shoot-through only if the programmed dead time is sufficient to allow the transition from completely on and off (Figure 2). But what happens if this time is too long? MOSFETs have a parasitic body diode that will clamp the switch node and prevent reverse breakdown while the FET is still off. This temporary V_F × I_DS power loss eats into efficiency the longer it takes for the FET to turn fully on and replace the (typically 0.8 V to 1.0 V) V_F × I_DS power loss product with the I_DS ² × R_DS(ON) loss, which is much lower. GaN FETs, on the other hand, do not have this body diode structure. They will clamp under reverse voltage at a much higher potential, with 2 V typical for the lateral transistor structure. This means that excessively high power losses will be incurred for even moderate dead times, making it essential for GaN FET controllers to minimize dead time. To overcome this, MOSFET-based designs often place a Schottky diode across the synchronous switch in parallel with the MOSFET to reduce the forward voltage drop during dead time. The diode’s junction capacitance, however, quickly dominates as a source of loss in the higher switching frequency applications GaN is ideal for. The trade-offs associated with these considerations are shown in Table 1.

GaN-based designs are now seemingly between a proverbial rock and a hard place. Shoot-through from dead time failure and the switches instantly evaporate; too much dead time and they could de-solder themselves right off the board. How does one determine the right balance between efficient conversion and an adequate safety margin? Perhaps the easiest way to solve this dilemma is to choose a converter that offers smart near-zero dead times or adaptive dead time features baked into the silicon. The LTC7890 and LTC7891 step-down controllers are dual-/single-buck designs that are purpose built to drive GaN FETs with pin selectable smart near-zero, adaptive, and precision resistor adjustable dead time control options. The architecture cleverly measures the actual V_GS and V_SW levels to intelligently control timing to achieve both precision and safety for any device being driven. It does this by making rapid adjustments to control a precise amount of dead time. Instead of the traditional open-loop gate drive, the programmed dead time is adjusted on the fly to guarantee turn-on and turn-off occurs when the controller needs, rather than when the gate signal along with parasitic gate resistance and capacitances dictate. This minimizes the reverse conduction losses and capitalizes on the near-zero reverse recovery loss inherent to GaN. A complete guide to these modes of operation is shown in Table 2. All that is left for the user is to verify that the programmed mode and timing are implemented correctly. However, the verification process presents challenges the designer must first overcome.

Measurement and Layout Considerations

Measuring the dead time and overshoot waveforms requires careful attention to probing techniques and implementation. GaN FETs have very stringent V_GS constraints relative to MOSFETs—typically 5 V with +6 V to –4 V ABS_MAX. Strong gate drive with parasitic reactive elements leads to ringing, and even brief excursions can damage GaN devices. The GaN gate presents a lower capacitance to the drive pin than MOSFETs, which is what makes them compelling for use at higher frequencies. However, probes themselves present parasitic reactance elements that can distort the waveform and give incorrect information about what the gate sees unprobed. Holding a probe with the hand using minimal hardware can be an invitation for disaster should the hand slip. Using the traditional alligator clip lead is out of the question. Classically, custom pigtail application probing techniques have been recommended for good scope measurements, provided the return path is properly chosen for top gate and switch nodes (Figure 3). This still leaves the floating top gate with a problematic approach for probing. One solution is to use a connector such as the MMCX style, or header pins that will adapt to MMCX probe tips. While the bottom gate can be ground referenced, the topside gate is referenced to switch, so some form of isolated probe must be used. Optical probes, such as the Tektronix TIVP or newer TICP, which features less drift, can provide this isolation for the top gate measurement and utilize the MMCX connector. Figure 4 shows a typical LTC7891 dead time measurement setup in progress with the MMCX connector directly under the FET gate pin coupled to a 1 GHz optical probe.

The connectors themselves are a case study in compromise. Surface-mount MMCX connector placement can take up physical board space. This is a concern where very tight layouts for power density are an issue. If the connector is placed (optimally) directly across the gate and source pins of the FET without introducing additional gate trace, it may spread the layout more than desired. On the other hand, placing the connector out of the way of the layout introduces additional trace inductance and resistance that can degrade measurement accuracy. Another alternative is the use of hole-through headers that can be populated only for measurement and then left off for the final build, but this entails using an adapter that increases parasitic elements slightly, along with creating annulus space openings on all layers in the pad stack. With the optimum balance of trade-offs and careful attention to layout, a minimal amount of overshoot and ringing due to the probe parasitic elements can be achieved (Figure 5). The red outlined original layout had the MMCX connector solidly connected to the switch node and gate node connected with via and inner trace to the gate pad of the GaN FET. The red trace showed ringing exceeding +6.4 V/–9.1 V. Using the same 2.2 Ω pull-up/1.0 Ω pull-down gate resistance but modifying the blue outlined layout to separate the MMCX body from the switch node and Kelvin connect it instead, the blue trace shows +2.4 V/–1.8 V of ringing at the top gate turn-off. The key takeaway here is that even minor adjustments to the layout can have great impact on the measured overshoot figure, which is a key parameter for tuning out overshoot and ensuring that the GaN FETs are not being overdriven.

Once the measurement technique is validated, the process of verifying dead time can begin. The first step is always to ensure that whatever type of probe being used to measure the top waveform is de-skewed with respect to the bottom signal using a common signal source. Dead time is relative, so the skew of one channel with respect to the other does not matter so long as a common signal shows up without any horizontal offset. This also allows for ensuring that any gain error and offset (common issues with optical probes) are corrected for, or at least known for, post-measurement adjustment later. Optical probes should be allowed to thermally stabilize before collecting data that is used to make decisions. It is often useful to record any gain and offset settings.

A baseline measurement at the lowest possible stress voltage and current (lower V_IN for buck, higher V_IN for boost) should be taken before pushing the limits of power on the design once the setup is completed. Gate overshoot scales as a function of input voltage and output current, so if the design is marginal, it’s best to discover and correct for this before stressing any limits. If the oscilloscope used for testing has reference cursors, it is helpful to place these at the upper and lower limits of the GaN VG data sheet spec as a visual cue for tolerable ranges. Use the switch node waveform to trigger and overlay top and bottom gate waveforms to get the optimal picture of dead time. Ideally a differential or optical probe is used to measure top gate waveforms. If the measurement must be made with respect to ground, it is often helpful to use scope trace math functions (if available) to subtract switch node from top gate node inputs to have a virtual ground-based trace for analysis.

Conclusion

Proper techniques for laying out, probing, and collecting data outlined here should provide system designers with a good degree of confidence in the robustness of GaN-based designs implemented with the LTC7890 and LTC7891 step-down controllers. Once a prototype has been set up to accurately measure the switching waveforms on the bench, the designer can choose a configuration and then optimize the gate drive signals. This will be covered in “Smart GaN Buck Controller Designs—Part 2: Configuration and Optimization.”

著者

James R. Staley

James R. Staleyは、アナログ・デバイセズのシニア・プロダクト・アプリケーション・エンジニアリング・マネージャです。産業用機器や高精度の計測器向けの電源システムを担当しています。半導体業界での経験は25年以上。Linear Technology（現在はアナログ・デバイセズに統合）とアナログ・デバイセズで、アプリケーション・エンジニアリング、セールス・アプリケーション・エンジニアリング、システム・エンジニアリングの業務を担当してきました。ノースカロライナ州立大学でナノテクノロジーを専攻。電子工学の学士号を取得し、Eta Kappa Nuとして卒業しました。ノースカロライナ州ローリーで家族と共に暮らしています。