- Ultra Low Noise Floor: -155 dBc/Hz @ 2 GHz
- LVPECL, LVDS, CML & CMOS Compatible Inputs
- Up to 8 Differential or 16 Single-Ended LVPECL Outputs
- One Adjustable Power CML/RF Output
- Serial or Parallel Control, Hardware Chip-Enable
- Power-Down Current < 1 µA
The ADH987S 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with fast rise / fall times. The low skew outputs of the ADH987S, combined with its fast rise / fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs / DACs or SERDES devices. The noise floor is particularly important in these applications, when the clock network bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the ADH987S have a noise floor of -155 dBc/Hz.
The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.
Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.
- Clock Distribution
- Clock Fanout
- LO Distribution
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.