- Fractional-N PLL up to 18GHz
- Low system phase noise of 0.35 ps rms @ 12GHz
Figure 1. Low Noise Microwave Fractional-N PLL (Simplified Schematic: All Connections and Decoupling Not Shown)
Loop Filter Design
The PLL loop filter design was done using Analog Devices free simulation tool, ADIsimPLL. This tool allows the design and simulation of several passive and active PLL loop filter topologies and has a library of Analog Devices op amps built in, which include the important op amp specifications such as voltage and current noise, input offset and bias currents, and voltage supply range. The simulation tool accurately predicts PLL closed loop phase noise and is able to model the effect of op amp noise along with the noise of the other PLL loop components. The ADIsimPLL simulation design file for this circuit note can be found at www.analog.com/CN0174_ADIsimPLL.
An inverting topology with pre-filtering was chosen. Pre-filtering is advisable so as not to overdrive the amplifier with the very short current pulses from the charge pump—which could slew rate-limit the input voltage. When using the inverting topology, it is important to make sure that the PLL IC allows the PFD polarity to be inverted, canceling out the op amp’s inversion, and driving the VCO with the correct polarity. The ADF4156 PLL has this PD polarity option.
Setup and Measurement
The settings used for the circuit are given in Table 1. Measured results are shown in Figure 2 versus the simulated performance as predicted by ADIsimPLL. As can be seen the results agree quite well. The measured integrated phase noise is 0.35 ps rms. The measurement setup is shown in Figure 3.
Table 1. Test Measurement Settings
| RF Frequency
| ADF4156 RF input frequency
| PLL Loop Filter Bandwidth
| Reference Input Frequency
| PFD Frequency
| Charge Pump Setting
| PD Polarity Bit
| Noise Mode
|| Low Noise