Abstract

If a system encounters errors that are not detectable by the watchdog timer or any faults other than the undervoltage fault, it is important to have an option to manually intervene or trigger the reset in a watchdog timer or supervisor. This application note explains how to incorporate the manual reset (MR) functionality to MAX16154 and MAX16155, a family of nanoPower^™ watchdog timer ICs that provide dynamic watchdog disable/enable option, along with the added benefit of acting as a supply voltage supervisor.

Introduction

It is often preferred to have a watchdog timer function that has a voltage monitor as well as a manual reset (MR). Manual reset is useful for microprocessor applications when the user needs to force reset. It is also useful in applications that need to reset when detecting a low voltage other than the main supply voltage. Manual reset offers full control over the reset rather than having only an undervoltage (UV) trigger. Memory errors and indefinite loops are two microcontroller errors that a watchdog timer cannot always detect and reset. For applications where this is unacceptable, it is important to use a watchdog timer that can be manually reset.

Introduction to the MAX16152–MAX16155 family of nanoPower Supervisors and Watchdog Timers

The MAX16152/MAX16153/MAX16154/MAX16155 are ultra-low-current supervisory circuits that monitor a single system supply voltage and assert an active-low reset signal when the supply voltage drops below the factory-trimmed reset threshold. After the supply voltage rises above the threshold voltage, the reset output remains asserted during the reset timeout period and finally asserts after the timeout period ends, and a watchdog timer circuit monitors microprocessor or microcontroller activity. During normal operation, the microprocessor or microcontroller toggles the WDI input periodically with a valid logic transition (low to high or high to low). If the WDI input is toggled within the watchdog timeout period, the internal timer is cleared and restarted, and the active-low WDO (WDOB) output remains high. If the input is not strobed before the timeout period expires, the watchdog output is asserted low for a period equal to the watchdog output pulse width. The MAX16152 and MAX16153 feature an active-low manual reset input (MRB) which allows an external pushbutton or logic signal to initiate a reset pulse. The MAX16154/MAX16155 feature a logic input (WD_EN) that allows the system to enable and disable the watchdog function as shown in Figure 1.

MAX16152–MAX16155 Features:

• 400nA (typ) Supply Current
• 1.2V to 5.5V Operating Supply Range
• Monitors Supply Voltage and Provides System Reset Signal
• 1.5V to 5V Input Threshold Range in 100mV Increments
• Watchdog Function Detects Faulty Code Execution
• Open-Drain Reset and Watchdog Outputs
• Watchdog Timer Enable Input
• 6-Bump WLP Package and 6-Pin SOT23 Package
• -40°C to +125°C Operating Temperature Range

Need for Dynamic Watchdog Enable Feature in a System

The watchdog timer in many of the available supervisory circuits in the market can be disabled by leaving the WDI pin open. In this mode, an internal signal is provided to periodically reset the watchdog timeout timer. But this often demands a tri-state buffer or proper initialization of the input. This could cause complications such as when a different three-state buffer is desired, the output leakage, when disabled, must not exceed the acceptable limits.

Applications that require a watchdog timer must ensure the software boot time does not exceed the minimum watchdog timeout period. If the boot time does exceed the watchdog timeout period, the application loops through the boot cycle indefinitely. This demands an option to disable the watchdog during power-up or provide options to have a startup delay feature.

Another situation where a dynamic-disable option of the watchdog timer is required is in systems with sleep mode. In applications such as IoT or wearables, sleep and other low-power modes complicate the implementation of watchdog timers. What should the watchdog do if the processor goes to sleep and stops executing? Should watchdog time stand still? This complication is cut down if the watchdog is handy or has a dynamic switchable on demand.

Proposed Solution to Incorporate Manual Reset (MR) in MAX16154/MAX16155

Manual RESET can be implemented by adding a voltage divider at VCC by utilizing the undervoltage detection where the manual reset trigger signal pulls the VCC below VTH. Various ways to drive or trigger a manual reset input in a system include controlling via mechanical switches or pushbuttons as well as buffers or digital logic as shown in Figure 2 and Figure 3.

Details of the Part Tested

Part Number             :   MAX16155CGAD+T
Threshold Voltage       :   1.7V, Measured VTH-  = 1.699V, VTH+ = 1.704V
RESET Timeout Period    :   128ms (typ.)
Watchdog Timeout Delay  :   64s (min.)
Watchdog Startup Delay  :   100ms (min.)

Global Conditions

Supply Rail Voltage (SRAIL) = 1.8V
Standard pulse generator with slew-rate control is used to replicate the logic device output.
All pullups are tied to the supply rail, not to VCC of the MAX16155.

Abbreviations

SRAIL   =   Supply  Rail Voltage
VCC_IC  =   MAX16155 VCC, Monitoring Input
RSTB    =   Active-Low RESET, Open-Drain Output, Pulled up to SRAIL
WDOB    =   Active-Low Watchdog Out, Open-Drain Output, Pulled up to SRAIL
WDI     =   Watchdog Input
WDEN    =   Dynamic WD Enable Input

Design Calculations and Considerations

• Figure 3 is considered for the explanation below.
• System rail is considered as 1.8V. VCC deviation typical 3% and worst-case deviation 5% considered.
• Hysteresis of MAX16154/MAX16155 = 0.4%.
• During MRB asserts, voltage at VCC should not fall below 1.2V, which is the minimum operating voltage of MAX16154/MAX16155.
• R3 must be lower to avoid RC delay by R3 and C1 at VCC. Consider 100?
• R3 + R4 should be higher to limit current during the MRB assert. If the sink current limit allows, make this sum lesser. Consider 680? and 100?
• For a maximum deviation of 5%, the V_CC rail can go up to 1.890V. During this voltage, the divider voltage should be below V_TH- when MRB is pulled low by the logic device.
• The trip voltage should be a minimum of 45mV below 1.8V considering the accuracy of V_TH.
• If V_CC = 1.8V, during MR asserts, V_CC at IC would be ~1.569V.

Bench Evaluation and Results

Test 1: MRB to RESETB Output Delay

Measure the delay from MRB falling edge to RESETB falling edge. The MRB fall-time is 1µs. MRB to RESETB delay is ~94µs, for an SRAIL of 1.8V.

Test 2: Manual RESET Releases and Deasserts the RESET

Measure the timeout period and observe the behavior of RESETB. MRB rise-time is 1µs. The RESETB timeout period is measured at 133.1ms, MRB via the function generator with a 1.8V voltage level.

Test 3: RESET Response to MR Trigger and Release

Conclusion

Manual reset (MR) is useful for microprocessor applications when the user needs to force reset. It gives full control over the reset rather than having only a low supply-voltage trigger or the watchdog timeout. In this application note, we reviewed how the manual reset (MR) functionality is easily enabled in the MAX16154/MAX16155, a family of nanoPower watchdog timer ICs that provide a dynamic watchdog disable/enable option, along with the added benefit of acting as supply voltage supervisors. Very low current consumption and tiny package size make these ICs ideal for multiple battery-powered applications including portable computing, metering, IoT, and medical wearables.