Applying Tee Networks to Extend the Solution Range for Photodiode Transimpedance Amplifier (TIA) Requirements—Part 2: Loop Gain Plot, Noise, and Single-Supply Operation

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Figure 1

   

Abstract

Part 1 showed a simplified compensation flow to the basic TIA design, then added a tee network to raise the required compensation capacitor above parasitic levels. In Part 2, the effect of that tee network on the circuit’s loop gain (LG) plot will be shown and how it maps back to the tee network design algebra.

Introduction

The tee network algebra of Part 1 can be illustrated by adjusting the terms in the loop gain (LG) plot. This gives a visual interpretation of what the tee network is doing. The effect the tee network has on the different output spot and integrated noise terms will then be assessed. The required circuit modifications to operate the TIA with the tee network using a single supply will be shown. Testing the tee in adapting a very demanding 50 MΩ TIA design will then be executed, raising the required feedback C_f to equal a typical 0.2 pF parasitic value.

Modifying the LG Plot Using the Tee Network

One way to approach the compensation solution for this tee network idea is to adjust each part of the original LG plot of Figure 2 in Part 1, including the effect of that inside the loop tee network. The adjustments to get the plot of Figure 1 include the following.

1. The low frequency noise gain shifts up to 20log(A_t).
2. The Z₁ frequency will move out in frequency by A_t as well.
3. The inside of the loop tee divider has effectively shifted the amplifier’s A_ol curve down by that amount. The entire A_ol curve shifts down by 20log(A_t).
4. Since Z₁ has shifted up the same amount the gain bandwidth product (GBP) has shifted down, the F_o frequency has remained the same.
5. Staying with the Butterworth target of setting P₁ = 0.707 × F_o, that frequency has not moved with the addition of the tee. Hence, using that lower R_f value now that we have some tee gain will shift the required C_f up—maybe into a realizable range for particularly challenging designs.
6. The higher frequency noise gain (NG) set by 1+ C_s/C_f has moved down by the A_t gain, which, along with the amplifier A_ol curve shifting down by A_t, places the F_c frequency at the same place as the design without the tee.

Applying these LG curve modifications to the example of Figure 5 in Part 1 using a tee gain of 2.78 adjusts the key elements on the LG curve to:

1. Low frequency noise gain goes up to 20log(2.78) = 8.9 dB.
2. Z₁ (1/2πR_fC_s) shifts out to 1.63 MHz (from a no tee 556 kHz, 2.78×).
3. The effective GBP shifts down to 1.3 GHz/2.78 = 467 MHz.
4. The geometric mean of Z₁ and GBP (F_o) stays the same at √1.63 MHz × 467 MHz = 27.6 MHz.
5. Set the feedback pole at the same 0.707 × F_o = 0.707 × 27.6 MHz = 19.5 MHz.
6. The higher C_f value reduces the higher frequency NG to 1 + 14.3 pF/1.2 pF = 13. That then intersects the lower GBP curve at the same F_c frequency F_c = 467 MHz/13 = 35.9 MHz. The tee gain has also shifted the minimum stable gain down to 10/2.78 = 3.6 where the new NG2 = 13 comfortably exceeds that.

Total Output Integrated Noise Using the Tee Network

The gains for each of the noise terms will be changed when going to the tee network, except for the op amps’ input current noise, which, by definition, will have the same resistive gain using the tee. The input spot voltage noise gets to the output times the noise gain curve, then is band limited either at the F_c frequency or by a lower bandwidth noise power bandwidth (NPBW) limiting postfilter. The tee will increase from a gain of 1 to a gain of A_t from low frequencies to the new noise gain zero frequency that is shifted up from the no tee location by the A_t gain. This will be an increased contribution using the tee, but this part of the output integrated noise is usually a very small part of the total and does not increase the total by more than 0.5%. The rising portion of the NG curve will add an equivalent spot noise for integration through P₁ that is identical to the original no tee design. If the NPBW is higher than the P₁ frequency (where the NG goes flat at the now reduced higher frequency NG set by 1 + C_s / C_f ), it is then gained up by the tee gain to be at the same output level and has the same flat span from P₁ to F_c.

The more significant part of the output integrated noise that is automatically increased by the tee network is the Johnson noise for the feedback resistor. Analyzing that terms’ spot noise with just the simple Rf resistor and then the solution using a tee network shows that it increases by a √A_t factor. Looking at the original spot noise voltage term due to the R_f noise will give:

Output spot noise due to the R_f Johnson noise (no tee):

Neglecting the small R2 term in the gain and output noise, going to the tee network reduces R_f by A_t, but then multiplies that spot noise by a linear A_t value. That adjustment is shown here, where R_f’ is the reduced R_f value, by A_t neglecting the small effect R2 has on the TIA gain and output noise.

From a spot noise perspective at the op amp output, the contribution of the original R_f Johnson noise has been increased by √A_t . Often, the resistor noise part of the total equivalent integrated output Vo rms is a small part of the total, and, if so, this adjustment will increase the total integrated noise only slightly. The R_f in these equations is the original desired gain.

In the example design (Figure 5, Part 1) with NPBW set to 20 MHz, the no tee design is dominated by the input current noise times the R_f gain, as 86% of the total output noise power. Going to the tee design, targeting C_f = 1.2 pF, increases the simulated integrated noise over 20 MHz from 330 µV rms with no tee to 351 µV rms (only 6%) as the Rf noise contribution increases from 6% of the total to 15% with that √A_t multiplier in its spot noise to the output.

Modifying the Design to a Single Supply

Most TIA designs operate from a unipolar output diode where the op amp is operating with a single supply, and the zero input output voltage is set just above the negative supply rail to keep the output stage out of saturation for a faster, more linear response. The easiest way to operate with an actual ground on the V+ input (part of the diode bias voltage) is to provide a small negative supply (such as –0.25 V) to give adequate headroom to the output stage for typical RR_OUT devices like the LT6200-10.

Lacking that negative supply, Figure 2 shows the design modified to a single 5 V supply with the inputs and output biased to approximately 0.25 V with no diode input current. With that offset on the V+ input, that same voltage will need to be applied to the bottom of the R1 resistor in the tee network to remove it as an output offset term. This nominal simulation shows 0.236 output DC bias. The V_BIAS source into R1 must show a low broadband output impedance with low noise for good broad-band TIA performance. Consider buffering Vbias into R1 using the ADA4899-1.

The small signal AC response of Figure 2 operating with a single +5 V supply has peaked at a very slight 0.25 dB and rolled off at 28.8 MHz—a very slight shift from the supply-centered response using split ±2.5 V supplies of Figure 6 in Part 1. This slight closed-loop response peaking over the balanced supply case is likely due to small shifts in the internal A_ol curve. That 0.25 dB peaking maps to a closed-loop Q = 0.8, where a nominal 9% step overshoot should be expected.

Producing a 0.25 V to 2.25 V output square wave at 2 MHz shows the waveform of Figure 4. This overshoots the expected 9% and shows a good reason to have a little extra headroom on the negative side to keep any overshoot from clipping into the negative supply. Adjusting the C_f up slightly can be used to reduce this overshoot. Any kind of post-NPBW filter can also be used to reduce this overshoot and should be considered in these designs to control the integrated noise.

Applying the Tee Network Using a JFET Input Device

To illustrate how useful this tee network technique might be, implement a 50 MΩ design from a 100 pF detector using the unity-gain stable AD8065 JFET input FastFET™ device. The design equations shown here apply equally as well to this unity-gain stable, 67 MHz GBP, very low input bias current device. For very high TIA gains, JFET or CMOS inputs are preferred to remove the output DC offset due to the input bias current through that feedback resistor. The simple design required a 0.1 pF C_f, too low for implementation. Targeting a 0.2 pF parasitic in the R_f resistor requires the tee design of Figure 5 where the R_f element has been reduced from 50 MΩ to 25.4 MΩ, and relatively low valued R1 and R2 elements provide 1.97 A_t gain. The expected F_-3dB in a Butterworth response was verified in this test simulation at the expected 44 kHz.

Note that there is no matching resistor on the V+ input to ground, as this JFET input device does not have matching input bias currents. The maximum 6 pA input bias current (25°C) adds only 6 pA × 50 MΩ = 0.3 mV to the output offset error. The 25°C max input offset voltage of 1.5 mV now adds 1.97 × 1.5 mV = 2.96 mV output offset error. Simulating the total output integrated noise through 30 kHz for the simple design shows 732 µV rms (input referred 14.7 pA rms) where the tee design increases to 743 µV rms—only a very slight increase since, in this design, the dominant noise term is the peaking NG times the 7 nV input voltage noise for the AD8065, which adds terms that do not really change going to the tee design.

Conclusion

Where a TIA design is asking for a possibly unrealizable low C_f value in the simple TIA design flow, using a resistive tee network is one simple option to raise the required C_f while providing the same gain and SSBW at the possible cost of a small increase in output integrated noise. This simple approach can also be used more generally to move the required C_f exactly onto standard C values for easier implementation. Be sure to account for the typical 0.20 pF parasitic on resistors. The tee network will also reduce the input common-mode voltage shift due to a bias current cancellation resistor on the V+ input used for bipolar input op amp solutions. Be sure to add a noise band limiting cap for that resistor into the V+ input if that bias current balancing resistor is used.

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