Startup Requirements for the MAX1452/MAX1455 Sensor Signal Conditioners


The MAX1452/MAX1455 are high-performance signal conditioners for sensors with analog voltage output. The signal conditioners can operate in both digital and analog modes. Typically, digital mode is used during transducer calibration, and the conditioner starts and operates in analog mode in the actual application. For a reliable startup in analog mode, the VDD and VDDF supplies must meet certain timing and profile requirements. This application note discusses these startup requirements, and gives guidelines for successful application of the devices.


The MAX1452 and the MAX1455 are high-performance signal conditioners with on-chip flash memory and temperature sensors. They operate in both digital and analog modes. The signal conditioners are compensated and programmed in digital mode during manufacturing, and start up and operate in analog mode in the application. Nonetheless, some users have reported that their signal conditioner starts up in digital mode while it has been configured to start in analog mode.

Setup for a Start in Analog Mode

To successfully start the MAX1452/MAX1455 in analog mode, the following three requirements must be satisfied:

  1. The MAX1452/MAX1455 must be configured to start in analog mode.
  2. The VDD supply must comply with some specific requirements.
  3. The VDDF supply must comply with some specific requirements.

  1. Configuring the MAX1452/MAX1455 to Start in Analog Mode

    1. The UNLOCK pin should be shorted to GND or be pulled to GND by an external pull-down resistor. [The UNLOCK pin has a weak internal pull-down resistor when the pin is left floating.] Using an external pull-down resistor allows the signal conditioner to be reprogrammed, if necessary, by applying VDD to the UNLOCK pin. The value of the pull-down resistor should be as small as possible to prevent unwanted triggering of UNLOCK pin by EMI or other external influences. 1kΩ is recommended.
    2. The low byte of the Control Register (or the Control Register location in the flash memory) must have a non-zero value. 0xFF is recommended.
  2. VDD Supply Requirement

    The VDD signal must rise from 0 to 4.5V within 0.2ms in a monotonic fashion. The VDD supply ramp must be oscillation free; at no time during the ramp-up should the signal be allowed to drop below 2V. If the VDD supply drops below 2V during ramp-up, it will interrupt the power-on reset (POR) signal propagation, and it will prevent successful retrieval of the Control Register data from the flash memory. An unsuccessful read of the Control Register data could cause the device to start in digital mode instead of the expected analog mode.

    Our tests and investigation of the VDD supply requirement on a large number of devices showed that these signal conditioners tolerate longer ramp-up times, with VDD rising linearly from 0 to 5V in as slow as 12ms. In all cases, the devices successfully started in analog mode. Successful startup of the signal conditioner in analog mode cannot, however, be guaranteed with VDD ramp rates slower than 0.2ms.

  3. VDDF Supply Requirements

    The VDDF supply powers the flash memory, and must be at the levels specified in the data sheet by the time the POR signal is released and the Control Register is accessed for the first time. The VDDF signal must follow the VDD signal within 10µs for successful reading of the Control Register from the flash memory at startup. As described in the MAX1452/MAX1455 data sheets, the lowest VDDF operating voltage over all conditions is 4.5V. Our tests showed that the flash memory will operate correctly with voltages as low as 3.5V. Operation of the flash memory at voltages below 4.5V cannot, however, be guaranteed.

    An RC filter on the VDDF supply (R between the VDD and VDDF pins, and C between the VDDF and GND pins) is typically used to dampen the effect of sudden current surges caused by flash-memory read operations. The flash-memory read operations update the temporary registers (five temporary registers feeding the five DACs) every 1ms (1kHz rate). The duration of high current draw is approximately 1µs with a peak value of 20mA. The overall effect of this current surge is insignificant, since the length of the high current draw is very short, only 1/1000 of the operating time. However, in the absence of an RC circuit on the VDDF pin, even for the most current-compliant power source, a significant drop in the VDDF and VDD supplies can occur. The drop in the VDD supply will propagate through the signal conditioner circuits and show up as noise on the output signal.

Other Considerations

  1. To completely turn off the signal conditioner and initiate a fresh startup, the VDD supply must be pulled below 1.5V before returning to a normal operating value.
  2. To operate the signal conditioner in digital mode with the Evaluation (EV) Kit software, execute the Find_port and Hard_init sequence after power is applied to the device. The Find_port function searches the system and finds an available serial port through which the signal conditioner communicates with the computer. The Hard_init function sets the communication baud rate between the signal conditioner and the computer to 28.8K (the baud rate can be changed later). The Find_port and Hard_init functions are part of the Serial.dll software that can be downloaded from the Analog website.
  3. The MAX1452/MAX1455 KEY, which is supplied as part of the EV Kit, is required for digital communication between the MAX1452/MAX1455 and the computer. In a typical setup, the KEY controls VDD applied to the signal conditioner. The communication software cycles power to the signal conditioner, through the KEY, to synchronize communication. Before cycling the VDD supply, the signal conditioner's temporary registers are read and then written back to the signal conditioner after the VDD is re-applied In effect, keeping the power cycling transparent from the user.


MAX1452 Data Sheet
MAX1452 User Manual
MAX1455 Data Sheet
MAX1455 User Manual