Design Note 454: Single-Ended to Differential Amplifier Design Tips

by Philip Karantzalis and Tim Regan Download PDF

Introduction

A fully differential amplifier is often used to convert a single-ended signal to a differential signal, a design which requires three significant considerations: the impedance of the single-ended source must match the single-ended impedance of the differential amplifier, the amplifier’s inputs must remain within the common mode voltage limits and the input signal must be level shifted to a signal that is centered at the desired output common mode voltage. 

In all cases, input impedance matching to the source impedance is necessary to prevent high frequency reflections. In designs where the single-ended source is DC coupled to a single supply differential amplifier, then level shifting and the common mode limits are also important considerations. The interaction of these three design parameters is non-trivial—component selection requires spreadsheet analysis using the equations described here.

Input Impedance Matching

If input AC coupling is used, then impedance matching is the only design issue. Figure 1 shows an example of a circuit matching a 50Ω single-ended source to an AC-coupled LTC6400-20 differential amplifier with a gain of 20dB set by internal resistors.

Figure 1. Impedance Matching for a Differential Amplifier with Fixed Gain Integrated Resistors.

The 66.5Ω resistor, RT, in parallel with the +IN input impedance, ZIN, matches the circuit input impedance to the 50Ω source. Differential balance is provided with the addition of the 28.7Ω resistor at the –IN input, R2. The balancing resistor assures equivalent feedback factors at the inputs, thus preventing large DC offsets.

To calculate the external resistor values, start by calculating ZIN. Then calculate RT for impedance matching and the value of the R2 for differential balance. The overall single-ended to differential gain (GAIN) must take into account the input attenuation of the RS and RT resistive divider and the effect of adding R2. In this example, the overall gain of the amplifier from signal source to differential output is only 4.44 even though the amplifier has a fixed gain of 10.

By AC coupling at the input, the amplifier’s input common mode voltage is equal to its output common mode voltage and the single-ended signal is automatically level shifted to an output differential signal centered on the output common mode voltage. 

If the input common mode voltage is not 0V, and the source cannot deliver the DC current into 116.5Ω (50Ω + 66.5Ω), then it is also necessary to AC couple the 66.5Ω resistor.

The DC Coupled Differential Amplifier

A general purpose, DC coupled, single-ended-to-differential amplifier circuit with source impedance matching and input level shifting is shown in Figure 2. Level shifting is provided by the reference voltage (VREF). If VREF is set to be equal to the input common mode voltage (VINCM) then the single-ended input signal is shifted to a differential signal centered on the output common mode voltage (VOCM).

Figure 2. Impedance Matching and Level Shifting for a Differential Amplifier with Gain Set By External Resistors.

The design of a single-ended to differential amplifier with external resistors provides an additional design option: specifying the amplifier gain. Figure 2 shows the design equations when the RF and R1 resistors are selectable, not fixed.

The design of this circuit begins with the value of R1. This resistor must be larger than the input source resistance but not so large as to increase circuit noise. Next, calculate the value of the feedback resistor RF using the desired gain (GN). Then calculate the value of resistors RT and R2.

Figure 3 shows an example of a single-ended-to-differential amplifier matching a 75Ω source and level shifting from a 2.5V input common mode to a 1.25V output common mode voltage (typical level shifting required from a 5V single-ended circuit to a 3V differential circuit to drive a high speed ADC). The single-ended-to-differential gain of the Figure 3 amplifier is 2 (the 1VP-P input signal is amplified into a 2VP-P differential output signal, a typical input voltage range of a high speed ADC). 

Figure 3. Putting it All Together: A 133MHz Differential Amplifier with External Gain Setting Resistors, Impedance Matching to a 75Ω Source and Shifting from 2.5V to 1.25V.

For linear operation, the amplifier’s input common mode limits must not be exceeded. Figure 2 shows the calculations for the bias voltage (VT) of the input T-network (RS, RT and R1) and the common mode voltage at the differential amplifier’s inputs. For example, in Figure 3, the 1.99V to 2.44V at the amplifier’s inputs (as calculated by the VA equation) is well within the rail-to-rail input common mode range of the LTC6406 (0V to V+).

Table 1. Sample of LTC High Speed Differential Amplifiers
Amplifier GBW
GHz 		  Slew Rate
V/μs		 Voltage Noise
nV/√Hz
 Gain
V/V
LTC6400-26
 1.9 6670 1.5 20
LTC6400-20
 1.8 4500 2.1 10
LTC6400-14
 1.9 4800 2.5 5
LTC6400-8
 2.2 3810 3.7 2.5
LTC6401-20 1.3 4500 2.1 10
 LTC6401-14 2 3600 2.5 5
LTC6404-1 0.5 450 1.5 R SET
LTC6404-2 0.9 700 1.5 R SET
LTC6405 2.7 690 1.6 R SET
LTC6406 3 630 1.6 R SET

Authors

Philip Karantzalis

Philip Karantzalis

Philip Karantzalis has worked in testing and designing analog signal circuits and systems since 1973. In 1986, he joined the Analog Devices Signal Conditioning Group providing baseband signal designs for data acquisition, RF modulators, demodulators and mixers, ADCs, and high accuracy test systems. Philip is currently a senior applications engineer with the Precision Systems Group of Analog Devices. He is a graduate of RCA Institutes of Electronics in New York City and has studied advanced mathematics at San Francisco State University.

tim-regan

Tim Regan

Tim Regan is Linear Technology’s manager of applications for signal conditioning products (amplifiers, comparators, filters, precision references, timing functions and RF circuits). He has provided applications assistance on all manner of analog semiconductor devices at Linear & National Semiconductor since graduating in 1973 with a BSEE from DeVry Institute of Technology. Tim enjoys the occasional round of golf.