DS2780 Board Layout to Minimize Current Measurement Offset Error

Introduction

As with any coulomb-counting IC, proper board layout is important for maintaining accuracy when measuring current. The DS2780 compensates for any current-measurement errors related to gain, but cannot compensate for offset errors. To minimize current-measurement offset error, Dallas Semiconductor recommends circuit designers using the DS2780 follow the layout recommendations in this application note.

Application Circuit

Due to size restrictions in cell packs, components are typically mounted on only one side of the PCB. Also, narrow PCB widths normally limit TSSOP8 packages, like the DS2780, to mounting with package leads in-line with the PCB length. This severely limits component-mounting options. Figure 1 shows the ideal layout for the SNS and VSS traces. The sense resistor should be placed as close as possible to the IC, and the loop area between VSS and SNS should be kept to an absolute minimum to minimize stray inductance between the traces. Sometimes this cannot be accomplished on a single PCB plane. Figure 2 shows the optimum layout if VSS and SNS must be routed through a separate plane. Failure to limit PCB inductance can create A/D offset errors larger than the data sheet specification.

Summary

The DS2780 cannot adjust for offset error in current measurements caused by VSS impedance or VSS inductance. Circuit boards should be designed to minimize these effects by limiting the closed loop space between the VSS and SNS traces. Errors in gain can be corrected through software trim, so no specific layout rules for gain accuracy are required.