Features and Benefits
- 5Msps/Ch Throughput Rate
- Four Simultaneously Sampling Channels
- Guaranteed 16-Bit, No Missing Codes
- 8VP-P Differential Inputs with Wide Input Common Mode Range
- 82dB SNR (Typ) at fIN = 2.2MHz
- –88dB THD (Typ) at fIN = 2.2MHz
- Guaranteed Operation to 125°C
- Single 3.3V or 5V Supply
- Low Drift (20ppm/°C Max) 2.048V or 4.096V Internal Reference
- 1.8V to 2.5V I/O Voltages
- CMOS or LVDS SPI-Compatible Serial I/O
- Power Dissipation 40mW/Ch (Typ)
- Small 52-Pin (7mm × 8mm) QFN Package
The LTC2325-16 is a low noise, high speed quad 16‑bit successive approximation register (SAR) ADC with differential inputs and wide input common mode range. Operating from a single 3.3V or 5V supply, the LTC2325-16 has an 8VP-P differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. The LTC2325-16 achieves ±2LSB INL typical, no missing codes at 16 bits and 82dB SNR.
The LTC2325-16 has an onboard low drift (20ppm/°C max) 2.048V or 4.096V temperature-compensated reference. The LTC2325-16 also has a high speed SPI-compatible serial interface that supports CMOS or LVDS. The fast 5Msps per channel throughput with one cycle latency makes the LTC2325-16 ideally suited for a wide variety of high speed applications. The LTC2325-16 dissipates only 40mW per channel and offers nap and sleep modes to reduce the power consumption to 90μW for further power savings during inactive periods.
- High Speed Data Acquisition Systems
- Optical Networking
- Multiphase Motor Control
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Demonstration circuit 2395A features the LTC2325/ LTC2324/LTC2320 family. With up to 5Msps, these differential, multiple channel, 16-bit, serial, high speed successive approximation register (SAR) ADCs are available in a 52-lead QFN package. Each ADC has an internal 20ppm/°C maximum drift reference and an SPI-compatible serial interface that supports CMOS and LVDS logic. Note the demo board is configured for CMOS operation by default; see the note under JP8 for LVDS operation. The demo manual refers to the LTC2325, but applies to all members of the family, the only difference being the number of channels, the sample rate and/or the number of bits. The DC2395A demonstrates the DC and AC performance of the LTC2325 in conjunction with the DC890 PScope™ data collection board. Alternatively, by connecting the DC2395A into a customer application, the performance of the LTC2325 can be evaluated directly in that circuit.
Software & Systems Requirements
Tools & Simulations
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