HMC987 Data Sheet4/22/20151 M
Features and Benefits
- Ultra Low Noise Floor: –166 dBc/Hz @ 2 GHz
- LVPECL, LVDS, CML & CMOS Compatible Inputs
- Up to 8 Differential or 16 Single-Ended LVPECL Outputs
- One Adjustable Power CML/RF Output
- Serial or Parallel Control, Hardware Chip-Enable
- Power-Down Current < 1 uA
- 32 Lead 5mm × 5 mm SMT Package 25 mm2
The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of –166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth.
The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps.
Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface.
- SONET, Fibre Channel, GigE Clock Distribution
- ADC/DAC Clock Distribution
- Low Skew and Jitter Clock or Data Fanout
- Wireless/Wired Communications
- Level Translation
- High Performance Instrumentation
- Medical Imaging
- Single-Ended to Differential Conversion
Markets and Technologies
Product Lifecycle Last Time Buy
All products in this family will be obsolete soon. Please contact ADI Sales or Distributors to arrange for final purchases and read our Obsolescence Information to review the time periods for placing final orders and receiving final shipments.
Evaluation Kits (1)
The HMC987LP5E Evaluation board can be controlled via parallel port or SPI (Serial Port Interface). Parallel port control is implemented by simple jumper settings on the evaluation board. Serial Port interface offers more flexibility. This HMC987LP5E Evaluation Kit also includes the PC compatible software with Graphical User Interface (GUI), and software drivers necessary for Serial Port Interface, allowing the user to read from and write to all device registers, set gain levels and save & recall device configurations
The page contains ordering information for evaluating the HMC987LP5E.
The design files link includes the BOM, schematics, and Gerber files for the evaluation board.
Documentation & Resources
Semiconductor Qualification Test Report: BiCMOS-A (QTR: 2013-00235)10/29/2015816 K
Tools & Simulations
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|HMC987LP5E||Material Declaration||Reliability Data||32-Lead QFN (5mm x 5mm w/ EP)|
|HMC987LP5ETR||Material Declaration||Reliability Data||32-Lead QFN (5mm x 5mm w/ EP)|
|Wafer Fabrication Data|
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.