HMC859

The HMC859LC3 is a Divide-by-8 w/Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications.

All differential inputs to the HMC859LC3 are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be DC or AC coupled. Outputs can be connected directly to a 50 Ohm ground-terminated system or drive devices with CML logic input. the HMC859LC3 also features an ouput level control pin, VR, which allows for loss compensation or signal level optimization. The HMC859LC3 operates from a single -3.3 V supply and is available in ROHS-compliant 3x3 mm SMT package.

Applications

• High Speed Frequency Divider (up to 26 GHz)
• Clock Synthesis
• Phase Locked Loops
• Broadband Test & Measurement

To request data sheet and for additional information, please contact RFMG-hsl@analog.com