The HMC859LC3 is a Divide-by-8 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC859LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.

All input signals to the HMC859LC3 are terminated with 50 Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ω to a non-ground DC voltage. The HMC859LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS compliant 3x3 mm SMT package.

APPLICATIONS

• High Speed Frequency Divider (up to 26 GHz)
• Clock Synthesis
• Phase Locked Loops
• Broadband Test & Measurement