AD6620

NOT RECOMMENDED FOR NEW DESIGNS

65MSPS Digital Receive Signal Processor

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Overview

  • High Input Sample Rate
    67 MSPS Single Channel Real
    33.5 MSPS Diversity Channel Real
    33.5 MSPS Single Channel Complex
  • NCO Frequency Translation
    Worst Spur Better than –100 dBc
    Tuning Resolution Better than 0.02 Hz
  • 2nd Order Cascaded Integrator Comb FIR Filter
    Linear Phase, Fixed Coefficients
    Programmable Decimation Rates: 2, 3 . . . 16
  • 5th Order Cascaded Integrator
    Comb FIR Filter
    Linear Phase, Fixed Coefficients
    Programmable Decimation Rates:
    1, 2, 3 . . . 32
  • Programmable Decimating RAM
    Coefficient FIR Filter
    Up to 134 Million Taps per Second
    256 20-Bit Programmable Coefficients
    Programmable Decimation Rates:
    1, 2, 3 . . . 32

Analog Devices' innovative Diversity Receiver chipset delivers two IF-to-baseband diversity channels in a compact, comprehensive solution that incorporates Automatic Gain Control, Received Signal Strength Indicator, high-resolution. Numerically Controlled Oscillator and digital filtering on-chip.

The chipset comprises Analog Devices' AD6600 dual-channel IF sampling analog-to-digital converter and AD6620 dual-channel decimating receiver chip. Configured with the appropriate external components, it can address a variety of air interface standards, including GSM, CDMA, IS136 and PHS, as well as proprietary modulation schemes for paging systems and wireless fixed access receivers.

Based on Analog Devices' next-generation receiver architecture, the Diversity Receiver replaces sensitive analog filters with digital filters for significant cost and size reductions. Complete reference designs show the optimal layout for reducing noise and minimizing cross-channel coupling.

AD6620
65MSPS Digital Receive Signal Processor
AD6620-fbl
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