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Features
- 100 MHz (10.5 ns) Core Instruction Rate
- Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units
- 570 MFLOPS Peak and
380 MFLOPS Sustained Performance (Based on FIR) - Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing
- EEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation
- Zero-Overhead Looping and Single-Cycle Loop Setup, Providing Efficient Program Sequencing
- 400-Ball 27 × 27 mm Metric PBGA Package
- Single Instruction Multiple Data (SIMD) Architecture provides two computational processing elements, concurrent execution and code compatibility at assembly level with the ADSP-2106x SHARC DSP family
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The ADSP-21160N SHARC® DSP is the second iteration of the ADSP-21160. Built in a 0.18 micron CMOS process, it offers higher performance and lower power consumption than its predecessor, the ADSP-21160M. Easing portability, the ADSP-21160N is application source code compatible with first generation ADSP-2106x SHARC DSPs in SISD (Single Instruction, Single Data) mode. To take advantage of the processor’s SIMD (Single Instruction, Multiple Data) capability, some code changes are needed. Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21160N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks.
The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD) processing. Using two computational units (ADSP-2106x SHARC DSPs have one), the ADSP-21160N can double performance versus the ADSP-2106x on a range of DSP algorithms.
The ADSP-21160N continues SHARC’s industry-leading standards of integration for DSPs, combining a high-performance 32-bit DSP core with integrated, on-chip system features. These features include a 4M-bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels, two serial ports, six link ports, external parallel bus, and glueless multiprocessing.
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ADSP-21160N
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ADSP-21160M/ADSP-21160N: SHARC Digital Signal Processor Data Sheet (Rev.D)
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Application Note 35
EE-110: A Quick Primer on ELF and DWARF File Formats
EE-332: Cycle Counting and Profiling (Rev.2)
EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev.2)
EE-160: Examining ADSP-21160 Link Port Backward Compatibility to the ADSP-2106x Link Ports
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++
EE-305: Designing and Debugging Systems with SHARC Processors (Rev.1)
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)
EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev.2)
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)
EE-134: Writing C Compatible Assembly Code Interrupt Handlers for the SHARC® Family
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)
EE-140: Using the ADSP-21160 Serial Ports in Multi-channel Mode
EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev.3)
EE-132: Placing C Code and Data Modules in SHARC memory using VisualDSP++™
EE-77: SHARC Link Port Booting
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)
EE-177: SHARC® SPI Slave Booting (Rev.3)
EE-195: Moving from the ADSP-21160M SHARC® DSP to the ADSP-21160N SHARC DSP
EE-104: Setting Up Streams with the VisualDSP Debugger
EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev.1)
EE-284: Implementing Overlays on ADSP-21160 SHARC® Processors (Rev.1)
EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs
EE-148: Introduction to SHARC® Multiprocessor Systems using VisualDSP++™
EE-106: Link Port Open Systems Interconnect Cable Standard
EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)
EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev.1)
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)
EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev.2)
EE-141: Benchmarking C Code on the ADSP-2106x and the ADSP-2116x Family of DSPs
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)
EE-112: Class Implementation in Analog C++
EE-340: Connecting SHARC® and Blackfin® Processors over SPI (Rev.1)
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| ADSP-21160NCBZ-100 |
400-Ball PBGA (27mm x 27mm)
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400-Ball PBGA (27mm x 27mm)
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PCN
Aug 23, 2023
- 23_0004
Assembly Site Transfer of Select PBGA Products to ASE Kaohsiung (AEG)
Jul 14, 2021
- 20_0165
Assembly Transfer of Select PBGA Products to ASE Chungli (AET)
Jun 18, 2010
- 07_0093
Conversion to Laser Mark for all ADSPXXXX, ADSSTXXXX, and PC Audio Codecs Ink on Plastic Encapsulated Parts
ADSP-21160NCBZ-100
Filter by Model
Part Models
Product Lifecycle
PCN
Aug 23, 2023
- 23_0004
Assembly Site Transfer of Select PBGA Products to ASE Kaohsiung (AEG)
Jul 14, 2021
- 20_0165
Assembly Transfer of Select PBGA Products to ASE Chungli (AET)
Jun 18, 2010
- 07_0093
Conversion to Laser Mark for all ADSPXXXX, ADSSTXXXX, and PC Audio Codecs Ink on Plastic Encapsulated Parts
Software & Part Ecosystem
Software & Tools Anomaly
Software Development Tools
CrossCore® Embedded Studio
Looking for Evaluation Software? You can find it here
Evaluation Kits 1
EMULATOR-USB & HP USB ICE
USB-Based Emulator and High Performance USB-Based Emulator
Features and Benefits
- Full speed USB 1.1 interface enabling download speeds of up to 150 KB/Sec (ADZS-USB-ICE) or High speed USB 2.0 interface enabling download speeds of up to 1.5MB/sec (ADZS-HPUSB-ICE)
- Background Telemetry Channel (BTC) support enabling non-intrusive data exchange at up to 2.0 MB/sec (ADZS-HPUSB-ICE only)
- 1.8V, 2.5V, and 3.3V compliant and tolerant
- Support for all ADI JTAG processors and DSPs
- 5V tolerant and 3.3V compliant for 5V processors and DSPs
- Multiprocessor support
- 14-pin JTAG connector
- 3-meter USB cable for difficult-to-reach targets
- CE-certified
Product Detail
The plug-and-play architecture of USB allows the emulators to be automatically detected and configured by the host operating system. It can also be connected to and disconnected from the host without opening the PC or turning off the power to the PC. A 3-meter cable is included to connect the emulators to the host PC, thus providing abundant accessibility to hard to reach targets.
The HP USB-based emulator also supports the Background
Telemetry Channel (BTC), a non-intrusive method
for exchanging data between the host and target
application without affecting the target system's
real-time characteristics.
Part Number:
USB-Based Emulator
Part Number: ADZS-USB-ICE
High Performance USB-Based Emulator
Part Number: ADZS-HPUSB-ICE
Tools Support:
Tel: 1-800-ANALOGD (262-5643)
Contact Support
For additional information, contact your local Analog Devices Sales Office or Distributor.
Resources
Tools & Simulations 3
IBIS Model 1
IBIS Model
SHARC Processors Software and Tools
BSDL Model File 1
