ADRF6655

Obsolete

Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO

Data Sheet (Rev. A) Product Selection Table

Viewing:

Overview

Broadband active mixer with integrated fractional-N PLL
RF input frequency range: 100 MHz to 2500 MHz
Internal LO frequency range: 1050 MHz to 2300 MHz
Flexible IF output interface
Input P1dB: 12 dBm

Input IP3: 29 dBm
Noise figure (SSB): 12 dB
Voltage conversion gain: 6 dB
Matched 200 Ω output impedance
SPI serial interface for PLL programming
40-lead 6 mm × 6 mm LFCSP

The ADRF6655 is a high dynamic range active mixer with integrated PLL and VCO. The synthesizer uses a programmable integer-N/fractional-N PLL to generate a local oscillator input to the mixer. The PLL reference input is nominally 20 MHz. The reference input can be divided by or multiplied by and then applied to the PLL phase detector. The PLL can support input reference frequencies from 10 MHz to 160 MHz. The phase detector output controls a charge pump whose output is integrated in an off-chip loop filter. The loop filter output is then applied to an integrated VCO. The VCO output at 2 × f_LO is then applied to a local oscillator (LO) divider as well as to a programmable PLL divider.

The programmable divider is controlled by an Σ-Δ modulator (SDM). The modulus of the SDM can be programmed between 1 and 2047.

The broadband, active mixer employs a bias adjustment to allow for enhanced IP3 performance at the expense of increased supply current. The mixer provides an input IP3 exceeding 25 dBm with 12 dB single sideband NF under typical conditions. The IIP3 can be boosted to ~29 dBm with roughly 20 mA of additional supplied current. The mixer provides a typical voltage conversion gain of 6 dB with a 200 Ω differential IF output impedance. The IF output can be externally matched to support upconversion over a limited frequency range.

The ADRF6655 is fabricated using an advanced silicon-germanium BiCMOS process. It is packaged in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP. Performance is specified over a −40°C to +85°C temperature range.

Documentation

This is the most up-to-date revision of the Data Sheet.

Software Resources

Evaluation Software 1

ADRF6655 Evaluation Board Software

ADRF6655 Evaluation Board Software (Rev. )

Can't find the software or driver you need?

Hardware Ecosystem

Parts	Product Life Cycle	Description
LDO Linear Regulators 1
ADP7104	RECOMMENDED FOR NEW DESIGNS	20 V, 500 mA, Low Noise, CMOS LDO

Tools & Simulations

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

Open Tool

ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

Open Tool

Evaluation Kits

ADRF6655 Evaluation Board

Buy Now View Details

Product Details

ADRF6655-EVALZ is a fully populated, 4-layer, FR4-based evaluation board. It requires 5 V/310 mA power supply for normal operation. The power supply should be connected to the clip leads, labeled VCC and GND. Another 3.2 V supply rail may be needed for IP3SET clip lead, which adjusts mixer core bias current. 3P3V_LDO and 2P5V_LDO clip leads each provide 3.3 V and 2.5 V LDO. All signal ports are populated with edge-mounted SMA connectors. RF port is the mixer RF input port configured for single-ended signaling. LO port provides the options to either output the LO signal generated by internal PLL or drive the mixer via an external LO source (see ADRF6655 data sheet for more information). OUT port is the mixer IF output port for single-ended signaling evaluation. IFP and IFN ports are the mixer IF output ports for differential interfacing evaluation. REFIN is the PLL reference input port. RFOUT port may be used to sense the device mux output. VTUNE port is avaiable for VCO control voltage if desired. The evaluation board is configued for operatioin as a broadband down-converter and features necessary footprints and prototype area for other various configurations, including up-conversion examples shown in the ADRF6655 data sheet. The evaluation board can be programmed through the USB port of a PC running Windows XP or Vista with Microsoft .NET Framework 3.5 installed. The required control software can be downloaded from www.analog.com.

Resources

ADRF6655 Gerber Files
9/18/2011

Software

ADRF6655 Evaluation Board Software
1.19 M

Latest Discussions

2 Years Ago