ADATE205

Obsolete

250 MHz Dual DCL

Data Sheet (Rev. A) Product Selection Table
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Overview

  • Driver, comparator, and active load with inhibit function
  • 250 MHz toggle rate
  • Dynamic clamps
  • Operating voltage range: −1.5 V to +6.5 V
  • Output voltage swing: 200 mV to 8 V
  • Four range adjustable slew rate
  • True/complement data mode bit
  • See Data Sheet for Additional Information

The ADATE205 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications. The active load can be powered down if not used.

The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state.

The driver has low leakage (<10 nA) in High-Z mode. The output voltage range is −1.5 V to +6.5 V to accommodate a wide variety of test devices.

The ADATE205 supports four programmable Tr/Tf times for applications where slower edge rates are required. The edge rate selection is done via two static digital CMOS select bits. The input data to the driver can be inverted using a single CMOS logic bit. This feature can be used for system calibration or applications where complement input data is needed.

Applications
  • Automatic test equipment
  • Semiconductor test systems
  • Board test systems
  • Instrumentation and characterization equipment

Alternative Part 2

ADATE318

600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip Calibration Engine

ADATE302-02

500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU

ADATE205
250 MHz Dual DCL
381138108ADATE205-fbl ADATE205-fbl
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Documentation

Obsolete Data Sheet 1

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Hardware Ecosystem

Parts Product Life Cycle Description
ADATE318
RECOMMENDED FOR NEW DESIGNS 600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip Calibration Engine
ADATE302-02
PRODUCTION 500 MHz Dual Integrated DCL with Differential Drive/Receive, Level Setting DACs, and Per Pin PMU
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