AD9684
Info : RECOMMENDED FOR NEW DESIGNS
searchIcon
cartIcon

AD9684

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter

Show More showmore-icon

Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 3
1ku List Price Starting From $349.25
Features
  • LVDS digital outputs
  • 1.1 W total power per channel at 500MSPS (default settings)
  • SFDR = 85 dBc at 170MHz fIN (500MSPS)
  • SNR = 68.6 dBFS at 170MHz fIN (500MSPS)
  • ENOB = 10.9 bits at 170 MHz fIN
  • DNL = ±0.5 LSB
  • INL = ±2.5 LSB
  • Noise Density = -153 dBFS/Hz at 500 MSPS
  • 1.25V, 2.50 V and 3.3V supply operation
  • No missing codes
  • Internal analog-to-digital converter (ADC) voltage reference
  • See data sheet for additional features
Additional Details
show more Icon

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.

The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.

Applications

  • Communications
  • Diversity multi-band, multi-mode digital receivers
    3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTE
  • General-purpose software radios
  • Ultrawideband satellite receiver
  • Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
  • Radar
  • Digital oscilloscopes
  • High speed data acquisition systems
  • DOCSIS CMTS upstream receive paths
  • HFC digital reverse path receivers
Part Models 3
1ku List Price Starting From $349.25

close icon
Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9684BBPZ-500
  • HTML
  • HTML
AD9684BBPZRL-500
  • HTML
  • HTML
AD9684BBPZRL7-1500
  • HTML
  • HTML
Software & Part Ecosystem

Software & Part Ecosystem

Can't find the software or driver you need?

Request a Driver/Software
Evaluation Kit

Evaluation Kits 2

reference details image

EVAL-AD9684

AD9684 Evaluation Board

zoom

EVAL-AD9684

AD9684 Evaluation Board

AD9684 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9684
  • SPI interface for setup and control
  • Wide band Balun driven input
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC
  • VisualAnalog® and SPIController software interfaces

Product Detail

The AD9684-500EBZ is an evaluation board for the AD9684, dual, 14-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALEZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPIController software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9684.

The AD9684 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and VisualAnalog and SPIController are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeedproductssupport@analog.com.

reference details image

HSC-ADC-EVALEZ

FPGA Based Data Capture Kit

zoom

HSC-ADC-EVALEZ

FPGA Based Data Capture Kit

FPGA Based Data Capture Kit

Features and Benefits

  • 256kB FIFO Depth
  • Supports multiple ADC channels via single FMC-HPC interface connector
  • JESD-204B support for up to eight (8) 6.5Gbps Lanes
  • Parallel input at 644 MSPS SDR and 1.2 GSPS DDR
  • Use with VisualAnalog® software
  • Based on Virtex-6 FPGA
  • Simple USB port interface (2.0)

Product Detail

The HSC-ADC-EVALEZ FMC-Compatible high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up and supports emerging serial interface standards, like JESD204B. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

Recently Viewed