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AD9549: Dual Input Network Clock Generator/Synchronizer Data Sheet (Rev. D)12/7/2010PDF1286 kB
Overview
Features and Benefits
- Flexible reference inputs
- Input frequencies: 8 kHz to 750 MHz
- Two reference inputs
- Loss of reference indicators
- Auto and manual holdover modes
- Auto and manual switchover modes
- Smooth A-to-B phase transition on outputs
- Excellent stability in holdover mode
- Programmable 16 + 1-bit input divider, R
- Differential HSTL clock output
- Output frequencies to 750 MHz
- Low jitter clock doubler for frequencies >
400 MHz - Please see Data Sheet for additional features.
Product Details
The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.
The AD9549 operates over an industrial temperature range of −40°C to +85°C.
APPLICATIONS
- Network synchronization
- Reference clock jitter cleanup
- SONET/SDH clocks up to OC-192, including FEC
- Stratum 3/3E reference clocks
- Wireless base stations, controllers
- Cable infrastructure
- Data communications
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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AN-0983: Introduction to Zero-Delay Clock Timing Techniques2/14/2015PDF162 kB
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AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015PDF291K
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AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)2/14/2015PDF0
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AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)2/14/2015PDF221 kB
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AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)2/14/2015PDF313 kB
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AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)2/14/2015PDF115 kB
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AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)2/14/2015PDF170 kB
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AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)12/6/2006PDF207 kB
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AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004PDF1679 kB
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FAQs7/26/2017
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RF, Microwave, and Millimeter Wave Product Selection Guide7/13/2018PDF9M
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Low-power direct digital synthesizer cores enable high level of integration2/20/2008
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Improved DDS Devices Enable Advanced Comm Systems9/1/2006
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ADI Buys Korean Mobile TV Chip Maker6/7/2006
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Design A Clock-Distribution Strategy With Confidence4/27/2006
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Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems12/7/2004
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Speedy A/Ds Demand Stable Clocks3/22/2004
Software & Systems Requirements
Tools & Simulations
Support & Discussions
AD9549 Discussions
Evaluation Boards
Pricing displayed is based on 1-piece.
Up to two boards can be purchased through Analog.com. To order more than two, please purchase through one of our listed distributors.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.