Features and Benefits
- SNR = 65 dB @ fIN up to 70 MHz @ 210 MSPS
- ENOB of 10.6 @ fIN up to 70 MHz @ 210 MSPS
- Excellent Linearity:
DNL = ±0.3 LSB (Typical)
INL = ±0.5 LSB (Typical)
- Two Output Data Options:
Demultiplexed 3.3 V CMOS Outputs Each @ 105 MSPS
Interleaved or Parallel Data Output Option
LVDS at 210 MSPS
- SFDR = 80 dBc @ fIN up to 70 MHz @ 210 MSPS
- 700 MHz Full Power Analog Bandwidth
- Power Dissipation = 1.3 W Typical @ 210 MSPS
- 1.5 V Input Voltage Range
- 3.3 V Supply Operation
- Output Data Format Option
- Data Sync Input and Data Clock Output Provided
- Clock Duty Cycle Stabilizer
The AD9430 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates up to a 210 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and reference are included on the chip to provide a complete conversion solution.
The ADC requires a 3.3 V power supply and a differential ENCODE clock for full performance operation. The digital outputs are TTL/CMOS or LVDS compatible and support either twos complement or offset binary format. Separate output power supply pins support interfacing with 3.3 V or 2.5 V CMOS logic.
Two output buses support demultiplexed data up to 105 MSPS rates in CMOS mode. A data sync input is supported for proper output data port alignment in CMOS mode and a data clock output is available for proper output data timing. In LVDS mode, the chip provides data at the ENCODE clock rate.
Fabricated on an advanced BiCMOS process, the AD9430 is available in a 100-lead surface-mount plastic package (100 e-PAD TQFP) specified over the industrial temperature range (-40°C to +85°C).
- Wireless and Wired Broadband Communications
- Cable Reverse Path
- Communications Test Equipment
- Radar and Satellite Subsystems
- Power Amplifier Linearization
- High performance. Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
- Low power. Consumes only 1.3 W @ 210 MSPS.
- Ease of use. LVDS output data and output clock signal allow interface to current FPGA technology. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 3.3 V supply simplifies system power supply design.
- Out of range (OR) feature. The OR output bit indicates when the input signal is beyond the selected input range.
- Pin compatible with 10-bit AD9411 (LVDS only).
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Documentation & Resources
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015
AN-282: Fundamentals of Sampled Data Systems2/14/2015
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)2/14/2015
AN-345: Grounding for Low-and-High-Frequency Circuits2/14/2015
AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0)2/14/2015
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012
AN-737: How ADIsimADC Models an ADC (Rev. B)11/9/2007
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/2007
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)12/14/2004
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004
AN-616: AD9430 Evaluation Board Modifications for XTAL Oscillator Clocking (Rev. 0)12/6/2002
AN-302: Exploit Digital Advantages in an SSB Receiver1/1/2000
Designing Power Supplies for High Speed ADC2/1/2012
Design A Clock-Distribution Strategy With Confidence4/27/2006
Advanced Digital Post-Processing Techniques Enhance Performance in Time-Interleaved ADC Systems8/1/2003 Analog Dialogue
Correlating High-Speed ADC Performance to Multicarrier 3G Requirements6/1/2003
LVDS Ups A/D Converter Data Rates10/7/2002
DNL and Some of its Effects on Converter Performance6/1/2001
Tools & Simulations
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
AD9430 IBIS Models
For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
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