AD6652
NOT RECOMMENDED FOR NEW DESIGNS12-Bit, 65 MSPS IF to Base Band Diversity Receiver
- Part Models
- 1
- 1ku List Price
- Starting From $56.45
Overview
- SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS)
- Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
- Sample rates up to 65 MSPS
- IF sampling frequencies to 200 MHz
- Internal ADC voltage reference
- Integrated ADC sample and-hold inputs
- Flexible analog input range (1 V to 2 V p-p)
- Differential analog inputs
- ADC clock duty cycle stabilizer
- 85 dB channel isolation/crosstalk
- Crossbar switched DDC inputs
- Digital resampling for noninteger decimation
- Programmable decimating FIR filters
- Flexible control for multicarrier and phased array
- Dual AGC stages for output level control
- Dual 16-bit parallel or 8-bit link output ports
- User-configurable built-in self-test (BIST) capability
- Energy-saving power-down modes
The AD6652 is a mixed-signal IF to baseband receiver consisting of dual 12-bit MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652 is designed to support communications applications where low cost, small size, and versatility are desired. The AD6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment.
APPLICATIONS
- Communications
- Diversity radio systems Multimode digital receivers:
GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,
IS95, IS136, CDMA2000, IMT-2000 - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
- Instrumentation and test equipment
PRODUCT HIGHLIGHTS
- Integrated dual 12-bit 65 MSPS ADC.
- Integrated wideband digital downconverter (DDC).
- Proprietary, differential SHA input maintains excellent SNR performance for input frequencies up to 200 MHz.
- Crossbar-switched digital downconverter input ports.
- Digital resampling permits noninteger relationships between the ADC clock and the digital output data rate.
- Energy-saving power-down modes.
- 32-bit NCOs with selectable amplitude and phase dithering for better than −100 dBc spurious performance.
- CIC filters with user-programmable decimation and interpolation factors.
- 160-tap RAM coefficient filter for each DDC channel.
- Dual 16-bit parallel output ports and dual 8-bit link ports.
- 8-bit microport for register programming, register read-back, and coefficient memory programming.
Documentation
Data Sheet 1
Application Note 3
Technical Articles 2
Analog Dialogue 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD6652BBCZ | 256-Ball CSPBGA (17mm x 17mm) |
This is the most up-to-date revision of the Data Sheet.