AD6624A

NOT RECOMMENDED FOR NEW DESIGNS

Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)

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Overview

  • 100 MSPS Wideband Input (14-Bit)
  • Four Independent Digital Receivers in a Single Package
  • Digital Re-sampling for non-Integer Decimation Rates
  • 3.3 Volt CMOS
  • Programmable Decimating RAM Coefficient FIR Filters
  • JTAG Boundary Scan, Built in Self Test (BIST) Capability

Designed for multicarrier, multimode receivers, the AD6624A is part of Analog Devices' SoftCellMulticarrier transceiver chipset. It is compatible with the latest IF-Sampling analog-to-digital converters including the AD6640, 12-bit and AD6644 / AD6645, 14-bit devices. The AD6624 is a four channel (quad) digital receiver signal processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter.

The AD6624A is available in a 196-Lead BGA package.

APPLICATIONS

  • Wireless Infrastructure:
    Cellular, PCS, In-Building, WLL GSM, IS-136, AMPS, PHS, EDGE
  • Phased Array Antenna Systems
  • Software Programmable Digital Receivers
  • Communications and Instrumentation

AD6624A
Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP)
AD6624A Functional Block Diagram
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Tools & Simulations

AD6624 (AD6624A) IBIS Models 2

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