AD10200
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AD10200

Dual Channel, 12-Bit, 105 MSPS IF Sampling A/D Converter With Analog Input Signal Conditioning

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Part Details
Features
  • Dual, 105 MSPS minimum sample rate
  • Channel-channel isolation, >80 dB
  • AC-coupled signal conditioning included
  • Gain flatness up to Nyquist: < 0.2 dB
  • Input VSWR 1.1:1 to Nyquist
  • 80 dB spurious-free dynamic range
  • Two’s complement output format
  • 3.3 V or 5 V CMOS-compatible output levels
  • 0.850 W per channel
  • Industrial and military grade
Additional Details
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The AD10200 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide-dynamic range ADCs. Each ADC has a transformer coupled front-end optimized for Direct-IF sampling. The AD10200 has on-chip track-and-hold circuitry, and utilizes an innovative architecture to achieve 12-bit, 105 MSPS performance. The AD10200 uses innovative high-density circuit design to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings.

The AD10200 operates with 5.0 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent encode and analog inputs. The AD10200 is packaged in a 68-lead ceramic chip carrier package. Manufacturing is done on Analog Devices, Inc. MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-H (–50°C to +125°C).

Product Highlights

  1. Guaranteed sample rate of 105 MSPS.
  2. Input signal conditioning with full power bandwidth to 250 MHz.
  3. Fully tested/characterized performance at 121 MHz AIN.
  4. Optimized for IF sampling.

Applications

  • Radar IF receivers
  • Phased array receivers
  • Communications receivers
  • Secure communications
  • GPS antijamming receivers
  • Multichannel, multimode receivers

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Documentation

Documentation

Technical Documents 24
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Tools & Simulations

Tools & Simulations 1

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