LT3077

The EVAL-LT3077-AZ evaluation board features the LT3077, a 3 A, ultra-low noise, high power-supply rejection ratio (PSRR), and 85 mV dropout ultra-fast linear regulator. The input voltage (V_IN) range for the V_IN power is from 0.6 V to 5.5 V. There are jumpers to set a 3-bit trilevel code that determines the output voltage (V_OUT) at pre-programmed levels that range from 0.5 V to 4.2 V. The maximum output current is 3 A. The EVAL-LT3077-AZ requires an external BIAS voltage (V_BIAS) that is at least 1.2 V higher than V_OUT and is between 2.375 V and 5.5 V.

The LT3077 of the EVAL-LT3077-AZ requires few external components, therefore, simplifying circuit design. External component choice, along with careful printed circuit board (PCB) design, helps optimize noise, PSRR, load transient response, and V_OUT regulation performance. The LT3077 requires capacitors for the internal reference, power input, BIASF pin, and power output. The internal reference is bypassed with a 16 V, 0805 sized, 4.7 μF capacitor to reduce output noise and program the soft-start. Larger capacitor case sizes and higher voltage ratings decrease 1/f noise for otherwise comparable capacitors. The 22 μF capacitor at the circuit output was chosen for high-frequency PSRR performance and to minimize V_OUT deviation during load transients.

The capacitor that bypasses the V_IN power for the LT3077 and the corresponding V_IN PCB layout can affect PSRR (see the Best PSRR Performance: PCB Layout for Input Traces section for additional information). The EVAL-LT3077-AZ decouples the V_IN power with a 47 μF capacitor. Less V_IN capacitance can improve PSRR at high frequencies (Refer to the LT3077 data sheet for the minimum capacitor value required for V_IN). Note that a bulk 220 μF tantalum polymer capacitor further reduces V_IN variation during load transients and reduces input voltage ringing that can be caused by inductive input power leads. The PCB has a footprint for an optional Subminiature Version A (SMA) connector that allows a shielded V_IN power connection to the PCB edge, if required.

The EVAL-LT3077-AZ bypasses the BIASF pin with a 2.2 μF capacitor instead of the V_BIAS supply input. Because the BIASF pin is isolated from VBIAS by a resistance that is internal to the LT3077, there is less PSRR degradation when BIASF is bypassed compared to when V_BIAS is bypassed. Otherwise, the effect on PSRR of the V_IN and V_BIAS bypass capacitors is similar. The EVAL-LT3077-AZ has resistors that allow a CURRENT LIMIT jumper to select output current limits of either 1.5 A or 3.72 A. The CURRENT LIMIT jumper can also disable external current-limit programming by shorting the ILIM pin to ground.

A POWER jumper (JP1) is available on the EVAL-LT3077-AZ to either connect the EN pin to V_BIAS to turn the output on or to ground to disable the output. There is a PG terminal that is pulled up to V_BIAS by a 51 kΩ resistor and pulled down by the open-drain, negative channel metal-oxide-semiconductor (NMOS) PG pin output for indication of regulator output status and other fault modes.

Banana jacks minimize voltage drops on V_IN and V_OUT connections. Bayonet Neill-Concelman (BNC) connectors provide low-noise connections to power V_IN, V_BIAS, and V_OUT. The EVAL-LT3077-AZ PCB design uses a split capacitor technique to Kelvin connect the ground terminal of the REF capacitor to the ground terminal of the output capacitor, and the SENSE pin to the positive terminal of the output capacitor. The VO+, VO −, and VI+ terminals Kelvin connect to V_IN and V_OUT and are the optimum place to observe output voltage regulation and dropout voltage performance. There are test points for BIASF and REF voltages.

The EVAL-LT3077-AZ has placeholders identified on the schematic as optional DNI components that make it convenient to add capacitance (see Figure 8).

For full details on the LT3077, refer to the LT3077 datasheet, which must be consulted with this user guide when using the EVAL-LT3077-AZ evaluation board.

The LT3077 of the EVAL-LT3077-AZ features an 18-Lead (3mm × 3mm) LFCSP-RT package. Proper board layout is essential for maximum thermal performance.

Design files are available on the EVAL-LT3077-AZ evaluation board page.