ADL5240

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100 MHz TO 4000 MHz RF/IF Digitally Controlled VGA

Data Sheet (Rev. A) Product Selection Table
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Overview

  • Operating frequency from 100 MHz to 4000 MHz
  • Digitally controlled VGA with serial and parallel interfaces
  • 6-bit, 0.5 dB digital step attenuator
  • 31.5 dB gain control range with ±0.25 dB step accuracy
  • Gain block or digital step attenuator can be first
  • Single supply operation from 4.75 V to 5.25 V
  • 31.5 dB gain control range with ±0.25 dB step accuracy
  • Gain block amplifier specifications
      Gain: 19.7 dB at 2.14 GHz
      OIP3: 41.0 dBm at 2.14 GHz
      P1dB: 19.5 dBm at 2.14 GHz
      Noise figure: 2.9 dB at 2.14 GHz
  • Low quiescent current of 93 mA
  • Thermally efficient, 5 mm × 5 mm, 32-lead LFCSP
  • The companion ADL5243 integrates a ¼ W driver amplifier to the output of the gain block and DSA

The ADL5240 is a high performance, digitally controlled variable gain amplifier (VGA) operating from 100 MHz to 4000 MHz. The VGA integrates a high performance, 20 dB gain, internally matched amplifier (AMP) with a 6-bit digital step attenuator (DSA) that has a gain control range of 31.5 dB in 0.5 dB steps with ±0.25 dB step accuracy. The attenuation of the DSA can be controlled using a serial or parallel interface.

Both the gain block and DSA are internally matched to 50 Ω at their inputs and outputs and are separately biased. The separate bias allows all or part of the ADL5240 to be used, which facilitates easy reuse throughout a design. The pinout of the ADL5240 also enables either the gain block or DSA to be first, giving the VGA maximum flexibility in a signal chain.

The ADL5240 consumes just 93 mA and operates from a single supply ranging from 4.75 V to 5.25 V. The VGA is packaged in a thermally efficient, 5 mm × 5 mm, 32-lead LFCSP and is fully specified for operation from −40°C to +85°C. A fully populated evaluation board is available.

Applications

  • Wireless infrastructure
  • Automated test equipment
  • RF/IF gain control
ADL5240
100 MHz TO 4000 MHz RF/IF Digitally Controlled VGA
ADL5240-FBL ADL5240-PC
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Documentation

Data Sheet 1

Evaluation Design File 1

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Software Resources

Evaluation Software 1

ADL5240 and ADL5243 Evaluation Board Software

 

Hardware Ecosystem

Parts Product Life Cycle Description
LDO Linear Regulators 1
ADP7102
RECOMMENDED FOR NEW DESIGNS 20 V, 300 mA, Low Noise, CMOS LDO
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Tools & Simulations

ADIsimRF

ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.

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ADIsimPLL™

ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.

Open Tool

Sys-Parameter Models for Keysight Genesys

Sys-Parameter models contain behavioral parameters, such as P1dB, IP3, gain, noise figure and return loss, which describe nonlinear and linear characteristics of a device.

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S-Parameter 1

Evaluation Kits

eval board
schematic 1
schematic 2
schematic 3
schematic 4
AD-FMCOMMS11-EBZ

Direct RF to Baseband Transmit Radio

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Features and Benefits

  • TX
    • 16-bit 12GSPS RFDAC
    • JESD204B Interface
      • 8 lanes up to 12.5Gbps
    • 1x/2x/4x/6x/8x/12x/16x/24x/32x Interpolation
    • 64-bit NCO at max rate
    • Analog Modes of Operation:
      • Normal Mode: 6GSPS DAC rate
        • Synthesis up to 2.5GHz (1st Nyquist)
      • Mix Mode: 6GSPS DAC rate
        • Synthesis in 2nd & 3rd Nyquist zones
      • 2X Normal Mode: 12GSPS DAC rate
        • Synthesis up to 6GHz (1st Nyquist)
      • Excellent dynamic performance
  • RX
    • 3.2GHz full power bandwidth at 2.5GSPS
      • Noise Density = -149.5dBFs/Hz, ENOB = 9.5 bits
      • SFDR = 77 dBc at 1GHz Ain (2.5Gsps)
      • SFDR = 77dBc at 1.8GHz Ain (2.5Gsps)
    • +/-0.3 LSB DNL, +/-1.0 LSB INL
    • Dual supplies : 1.3V and 2.5V
    • 8 or 6 Lane JESD204B Outputs
    • Programmable clipping threshold for Fast Detect output
    • Two Integrated wide band digital down converters (DDC) per channel
      • 10-bit complex NCO
      • 2 cascaded half band filters (dec/8, dec/16)
    • Timestamp for synchronous processing alignment
      • SYSREF Setup/Hold detector
    • Programmable Interrupt (IRQ) event monitor

Product Details

The AD-FMComms11-EBZ board is a system platform board for communication infrastructure applications that demonstrates the Direct to RF (DRF) transmitter and observation receiver architecture. Using high sample rate RFDAC(s) and RFADC(s), a number of components in previous generation transmitters can be eliminated, such as mixers, modulators, IF amplifiers and filters. The objective being to bring the ADC or DAC as close to the antenna as possible, leading to possibly more cost effective and efficient communications solution.

It is composed of multi-GSPS RF ADC and DAC, AD9625 and AD9162 respectively. The transmit path contains a balun, low pass filter, gain block and variable attenuation to produce an output appropriate for a power amplifier module. Along the observation path, the PA output is coupled back into the board through a variable attenuator, a balun and finally the ADC. Clock management is taken care of on board; all the necessary clocks are generated from a reference. Power management is present as well.

EVAL-ADL5240

ADL5240 Evaluation Board

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Product Details

ADL5240-EVALZ is a fully populated, 4-layer, Rogers 3003-based evaluation board. For normal operation, it requires a 5 V/200 mA power supply. The evaluation board can be programmed through the USB port of a PC running Windows XP or Vista with Microsoft .NET Framework 3.5 installed. The required control software can be downloaded from www.analog.com. The DSA and the amplifier can be individually biased to the clip leads labeled VCC, VDD and GND as well as connected to the VDD plane using R2 and R1. The evaluation board can be configured with AMP-driving-DSA or DSA-driving-AMP using the available resistor and capacitor pads.
AD-FMCOMMS11-EBZ
Direct RF to Baseband Transmit Radio
AD-FMCOMMS11-EBZ Block Diagram AD-FMCOMMS11-EBZ Evaluation Board AD-FMCOMMS11-EBZ Evaluation Board - Top View AD-FMCOMMS11-EBZ Evaluation Board - Bottom View
EVAL-ADL5240
ADL5240 Evaluation Board

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