AD4880

RECOMMENDED FOR NEW DESIGNS

Dual Channel 20-Bit, 40 MSPS, SAR ADC with Analog Front End

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Overview

  • Integrated fully differential ADC drivers
    • Wide input common-mode voltage range
    • High common-mode rejection
    • Single-ended to differential conversion
  • Gain options include: 1.03, 1.25, 1.53, 2.03, 2.74, 4.11, and 5.77
    • Integrated gain-setting resistors
  • High performance
    • 20-bit resolution, no missing codes
    • Throughput: 40MSPS per channel
    • Conversion latency: 46.25 ns
    • INL: ±7.5ppm (typical), ±12ppm (maximum)
    • SNR/THD
      • 92.6dBFS (typical)/−107.6dBc (typical) at fIN = 1 kHz
      • 91.2dBFS (typical)/−108.0dBc (typical) at fIN = 500 kHz
    • Noise spectral density: −160.9dBFS/Hz
  • Low power
    • 120.5mW per channel typical at 40 MSPS
  • Integrated, low-drift reference buffers and decoupling
  • Integrated VCM generation
  • Digital features and data interface
    • Conversion result FIFO, 16K samples per channel
    • Digital averaging filter with up to 210 decimation
  • SPI configuration per channel
  • Configurable data interface per channel
    • Single lane, DDR, serial LVDS, 800 MBPS per lane
    • Dual lane, DDR, serial LVDS, 400 MBPS per lane
    • Single/quad lane SPI data interface
  • Package
    • 196-ball, 10 mm x 10 mm CSP_BGA, 0.65 mm pitch
    • Integrated supply decoupling capacitors
  • Operating temperature range: −40°C to +85°C

20-bit, successive approximation register (SAR) analog-to-digital converter (ADC) with integrated fully-differential drivers (FDA) and gain-setting resistors. The two channels can be sampled either simultaneously or independently, which offers flexibility for a wide range of applications.

The integration of the ADC drivers, low drift reference buffers, low dropout (LDO) regulators along with all critical decoupling capacitors greatly simplifies analog front-end design challenges. Specified performance is easier to achieve, which requires a simpler and more compact printed circuit board (PCB) layout.

Optimized for input signals up to 1MHz, the AD4880 delivers low noise and exceptional linearity at remarkably low power consumption, which makes it ideal for many precision data acquisition systems.

Anti-aliasing filter requirements can be relaxed by taking advantage of the high sample rate to oversample, then apply integrated digital filtering and decimation to reduce noise and deliver an increase in dynamic range for applications where ultra-low latency is not required.

The AD4880 features a SAR architecture that results in a conversion latency of just 46.25ns. Therefore, it is a good fit for wide bandwidth applications that have multiplexed input signals, applications that require extremely low latency, or both. Such high throughput and low-latency applications can benefit from the two independent, multilane low-voltage differential signaling (LVDS) interfaces. Alternatively, the load on the digital host can be eased by storing the captured data in the on-chip, 16k samples per channel, first in, first out (FIFO) memory, then asynchronously accessing it via the serial-peripheral interface (SPI) data interfaces.

APPLICATIONS

  • Digital imaging
  • Cell analysis
  • Spectroscopy
  • High speed data acquisition
  • Digital control loops, hardware in the loop
  • Power quality analysis
  • Source measurement units
  • Nondestructive test

AD4880
Dual Channel 20-Bit, 40 MSPS, SAR ADC with Analog Front End
AD4880 Functional Block Diagram AD4880 Pin Configuration AD4880 Chip Illustration
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Tools & Simulations

LTspice


Models for the following parts are available in LTspice:

  • AD4880
LTspice

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.


Evaluation Kits

eval board
EVAL-AD4880

Evaluating the AD4880, Dual-Channel 20-Bit, 40MSPS, SAR ADC with Analog Front End

Features and Benefits

  • Fully-featured evaluation board for the AD4880
  • Analysis | Control | Evaluation (ACE) Software plug-in available for device configuration, data capture, and performance evaluation
  • Flexible analog front end
  • On-board power solution and precision reference
  • On-board clock generation circuitry with sampling frequency control via the ACE Software
  • FMC compatible

Product Details

The EVAL-AD4880-FMCZ evaluation board is designed to demonstrate the performance of the AD4880 dual channel ADC with integrated analog front end (AFE) and provide access to a limited set of features from the chip in the ACE Software environment. The EVAL-AD4880-FMCZ evaluation kit supports the following AD4880 features:

  • Low-voltage digital signaling (LVDS) data output interface.
  • Analog-to-digital converter (ADC) configuration via serial peripheral interface (SPI).
  • Internal or external generation of 1.1V regulated supply rails.
  • Sampling rate capability between 1.25MSPS and 40MSPS.

The EVAL-AD4880-FMCZ evaluation board is designed for use with the Digilent ZedBoard via the field programmable gate array (FPGA) mezzanine card (FMC) connector. The ZedBoard uses a Xilinx Zynq7000 system on chip (SoC) that runs Analog Devices Kuiper Linux and LIBIIO included on the SD card supplied in the evaluation board kit to facilitate communication with the EVALAD4880- FMCZ, enabling ADC configuration and data capture. The ZedBoard also provides the communication link to the host PC and the ACE Software plug-in.

Full specifications on the AD4880 are available in the AD4880 data sheet available from Analog Devices, Inc., and must be consulted with this user guide when using the EVAL-AD4880-FMCZ evaluation board.

For the current schematics, layouts, and bill of materials, refer to the EVAL-AD4880-FMCZ product page.

EVAL-AD4880
Evaluating the AD4880, Dual-Channel 20-Bit, 40MSPS, SAR ADC with Analog Front End
EVAL-AD4880 Evaluation Board Angle View EVAL-AD4880 Evaluation Board Top View EVAL-AD4880 Evaluation Board Bottom View

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