Synchronizing Multiple Fractional PLLs

Ultra-low jitter clocks play a serious role in modern communication, instrumentation and radar applications to get best performance. On top of the requirement for an ultra-low jitter clock, synchronization of multiple high frequency clocks (especially fractional PLLs) is the other challenge for the large converter array applications. This work collects all these challenges and provides and exceptional solution which is very easy to adapt. EZSYNC and Timed-SYNC concepts of the new Fractional PLL chips give the option for selection the most suitable synchronization method while providing the best-in-class jitter performance up to 12.8 GHz.