Can I access a nonstandard SPI interface with my MCU?
Yes, but it might take a little extra effort.
Many current precision analog-to-digital converters (ADCs) have a serial peripheral interface (SPI) or some serial interface to communicate with controllers including a microcontroller unit (MCU), a DSP, or an FPGA. The controllers write or read ADC internal registers and read conversion codes. SPI is becoming more and more popular due to its simple printed circuit board (PCB) routing and a faster clock rate compared to parallel interface. And, it is easy to connect an ADC to the controller with a standard SPI.
Some new ADCs have an SPI, but others have a nonstandard 3-wire or 4-wire SPI as a slave because they want to achieve a faster throughput rate. For example, the AD7616, AD7606, and AD7606B family has two or four SDO lines for faster throughput rate in serial mode. The AD7768, AD7779, and AD7134 families have multiple SDO lines and they work as SPI masters. Users tend to encounter difficulties in designing microcontroller SPIs for ADC configuration and code reading.
Standard MCU SPI Connection to an ADC
SPI is a synchronous, full-duplex, master/slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge. Both master and slave can transmit data at the same time. Figure 2 shows a typical 4-wire MCU SPI interface connection.
To begin SPI communication, the controller must send the clock signal and select the ADC by enabling the CS signal, which is usually an active low signal. Since SPI is a full-duplex interface, both the controller and ADC can output data at the same time via the MOSI/DIN and MISO/DOUT lines, respectively. The controller SPI interface provides the user with flexibility to select the rising or falling edge of the clock to sample and/or shift the data. For reliable communication between the master and the slave, users must follow the digital interface timing specifications of both the microcontroller and the ADC chip.
If the microcontroller SPI and ADC serial interface have the standard SPI timing mode, it is not a problem for users to design the PCB routing and develop the drive firmware. But there are some new ADCs with a serial interface port that is not a typical SPI timing pattern. It does not seem possible for the MCU or the DSP to read data through the AD7768 serial port, a nonstandard timing SPI port, as shown in Figure 4.
This article will introduce approaches to manipulating the standard microcontroller SPI to interface with ADCs that have nonstandard SPI ports.
This article will cover four different solutions to read the ADC codes by serial interface:
- Solution 1: MCU as SPI slave interfacing to ADC as SPI master by one DOUT line.
- Solution 2: MCU as SPI slave interfacing to ADC as SPI master by two DOUT lines.
- Solution 3: MCU as SPI slave interfacing to ADC as SPI master through DMA.
- Solution 4: MCU as SPI master and SPI slave to read data on two DOUT lines.
AD7768 Code Reading with STM32F429 Microcontroller SPI by One DOUT Line
As shown in Figure 4, when FORMATx = 11 or 10, Channel 0 to Channel 7 output data on DOUT0 only. In standard mode operation, the AD7768/AD7768-4 operates as the master and stream data to the MCU, DSP, or FPGA. The AD7768/AD7768-4 supplies the data, the data clock (DCLK), and a falling edge framing signal (DRDY) to the slave device.
The STM32Fxxx family of microcontrollers are widely used in many different applications. The MCUs have several SPI ports, which can be configured as SPI master or slave with typical SPI timing modes. The methods introduced in the following session can also be applied on other microcontrollers with an 8-bit, a 16-bit, or a 32-bit frame.
The AD7768/AD7768-4 have 8-channels and 4-channels, simultaneous sampling sigma-delta (Σ-Δ) ADCs, respectively, with a sigma-delta modulator and digital filter per channel, enabling synchronized sampling of ac and dc signals. They achieve 108 dB dynamic range at a maximum input bandwidth of 110.8 kHz, combined with typical performance of ±2 ppm INL, ±50 μV offset error, and ±30 ppm gain error. The AD7768/AD7768-4 user can trade off input bandwidth, output data rate, and power dissipation, and select one of three power modes to optimize for noise targets and power consumption. The flexibility of the AD7768/AD7768-4 allows them to become reusable platforms for low power dc and high performance ac measurement modules. Unfortunately, AD7768’s serial interface is not a typical SPI timing mode, and AD7768 works as the serial interface master. Generally, users must use FPGA/CPLD as its controller.
For example, 32F429IDISCOVERY and AD7768 eval boards are used. The workaround SPI wires are connected as shown in Figure 5. In this setup, all eight AD7768 channel data outputs on DOUT0 only.
Problems to be solved:
- AD7768 works as the SPI master, so the STM32F429I SPI must be configured as SPI slave.
- DRDY high pulse is just one cycle of DCLK duration that is not a typical CS.
- DCLK continuously outputs and DRDY is low when all the channel data bit output is finished.
Solution 1: MCU SPI as Slave Interfacing to SPI Master ADC by One DOUT Line
- Configure one of STM32F429 is SPI ports, like SPI4, as a slave to receive data bits on MOSI at DCLK.
- Connect AD7768 DRDY to the STM32F429 external interrupt input pin EXTI0 and NSS (SPI CS) pin. The rising edge of DRDY will trigger EXTI0 handler routine to enable the SPI slave to start to receive data bits from the first DCLK falling edge after DRDY goes to low. Timing design is critical here.
- After all the data from Channel 0 to Channel 7 are received, the SPI should be disabled to prevent reading in extra invalid data, since the DRDY makes SPI slave CS low and DCLK keeps toggling.
MCU Firmware Development Notes
With the software in interrupt mode, DCLK can run up to 4 MHz, and ODR 8 kSPS is achieved. The software should go into the interrupt handler to start SPI within one and a half DCLK period time (375 ns). To more easily enable the software to go into the interrupt routine, the MCU can read the data at the DCLK rising edge, which can give an additional half DCLK period time. But, since the t5 DCLK rise to the DOUTx invalid minimum is –3 ns (–4 ns for IOVDD = 1.8 V), a propagation delay (>|t5| + MCU hold time) on DOUTx should be added by PCB routing or buffer.
Solution 2: MCU SPI as Slave Interfacing to SPI Master ADC by Two DOUT Lines
In the first solution, only DOUT0 is used to output all the 8-channel data. So, the data reading limits the ADC throughput rate to 8 kSPS. As shown in Figure 1, Channel 0 to Channel 3 output on DOUT0 and Channel 4 to Channel 7 output on DOUT1 can reduce the data transfer time. The serial wires are connected as shown in Figure 7. With such improvement, the ODR can easily go up to 16 kSPS at DCLK 4 MHz.
The firmware can use polling mode instead of the interrupt mode to reduce the time latency from the DRDY rising edge trigger to enable the SPI to receive the data. This can achieve ODR 32 kSPS at DCLK 8 MHz.
Solution 3: MCU SPI as Slave Interfacing to SPI Master ADC Through DMA
Direct memory access (DMA) is used in order to provide high speed data transfer between peripherals and memory, and between memory and memory. Data can be quickly moved by DMA without any MCU action. This keeps MCU resources free for other operations. Here are the design notes for an MCU SPI acting as slave to receive data through DMA.
Solution 4: MCU SPI as Master and Slave to Read Data on Two DOUT Lines
The high throughput or multichannel precision ADCs provide SPI ports with two, four, and even eight SDO lines for faster code reading time in serial mode. For microcontrollers with two or more SPI ports, they can concurrently run the SPI ports for faster code reading.
In the following use case, 32F429IDISCOVERY uses SPI4 as SPI master and SPI5 as SPI slave to receive EVAL-AD7606B-FMCZ data on DOUTA and DOUTB as shown in Figure 8.
The AD7606B is a 16-bit, simultaneous sampling, analog-to-digital data acquisition system (DAS) with eight channels, each channel containing analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter, and a 16-bit successive approximation register (SAR) ADC. The AD7606B also contains a flexible digital filter, low drift, 2.5 V precision reference and reference buffer to drive the ADC and flexible parallel and serial interfaces. The AD7606B operates from a single 5 V supply and accommodates ±10 V, ±5 V, and ±2.5 V true bipolar input ranges when sampling at throughput rates of 800 kSPS for all channels.
Figure 13 shows the AD7606B digital interface capture of BUSY, SCLK, DOUTA, and DOUB running at 240 kSPS.
This article discussed approaches to using a microcontroller SPI to access ADCs with nonstandard SPI interfaces. These approaches can be used directly or with slight adjustments to control the ADC SPI, which is working as an SPI master or with multiple DOUT lines for a faster throughput rate.
Many thanks to applications engineers Mika Jiang and Yao Zhao for advice on the quick startup on the STM32F429IDISCOVERY kit and firmware debug jobs.
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